Pub Date : 2026-02-27DOI: 10.1109/LSSC.2026.3668876
Yihang Cheng;Yihan Zhang;Huaqiang Wu;Sining Pan
This letter presents an energy-efficient dynamic amplifier. It utilizes source-coupled input boosting and time-domain differential sampling techniques to boost the effective input signal by $4times $ compared to its floating inverter amplifier (FIA) prototype without noise or power penalties. With discharge-based dynamic biasing, the bandwidth (BW) and power of the amplifier can be scaled by $100times $ . Fabricated in a standard 0.18-$mu $ m CMOS technology, the amplifier achieves a state-of-the-art power efficiency factor (PEF) of 0.19, which is $16times $ better than that of a standard FIA. It also achieves a scalable BW/power range from 0.5 kHz/2.3 nW to 50 kHz/206 nW.
{"title":"A 0.19-PEF Bandwidth/Power Scalable Dynamic Amplifier","authors":"Yihang Cheng;Yihan Zhang;Huaqiang Wu;Sining Pan","doi":"10.1109/LSSC.2026.3668876","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3668876","url":null,"abstract":"This letter presents an energy-efficient dynamic amplifier. It utilizes source-coupled input boosting and time-domain differential sampling techniques to boost the effective input signal by <inline-formula> <tex-math>$4times $ </tex-math></inline-formula> compared to its floating inverter amplifier (FIA) prototype without noise or power penalties. With discharge-based dynamic biasing, the bandwidth (BW) and power of the amplifier can be scaled by <inline-formula> <tex-math>$100times $ </tex-math></inline-formula>. Fabricated in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology, the amplifier achieves a state-of-the-art power efficiency factor (PEF) of 0.19, which is <inline-formula> <tex-math>$16times $ </tex-math></inline-formula> better than that of a standard FIA. It also achieves a scalable BW/power range from 0.5 kHz/2.3 nW to 50 kHz/206 nW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"93-96"},"PeriodicalIF":2.0,"publicationDate":"2026-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147440659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a 5T2C pixel circuit for active-matrix (AM) micro-displays in near-eye display applications. The circuit supports monochrome micro light-emitting diode (micro-LED) displays with ultrahigh resolution of 7056 pixels per inch (PPI). The circuit is designed and fabricated based on medium-voltage (MV) devices from the 55-nm high-voltage (HV) CMOS process. The total storage capacitance is only 6.588 fF, and the stored charge is susceptible to transistor leakage current, resulting in significant deviations in the average driving currents. To mitigate the deviations, the circuit isolates the switching transistor (TS) from the data signals, increases the body voltage for TS, and minimizes the body area of TS. The low-leakage structure effectively reduces off-leakage current (IOFF) and reverse-bias p-n-junction leakage current (IREV) of the transistors. Simulation results demonstrate that the proposed circuit produces slight current deviations compared to a conventional 2T1C circuit. Measurement results also confirm that the deviation rate is less than 6.23% for all gray levels (GLs).
{"title":"A 7056-PPI Pixel Circuit With Low-Leakage Structure for Active-Matrix Monochrome Micro-LED Displays","authors":"Chih-Lung Lin;Cheng-Han Ke;Yu-Chang Chiu;Yuan-Yu Lai;Yi-Chien Chen;Cheng-Rui Lu;Yu-Hsiang Fu;Chih-Chuan Huang","doi":"10.1109/LSSC.2026.3667520","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3667520","url":null,"abstract":"This work presents a 5T2C pixel circuit for active-matrix (AM) micro-displays in near-eye display applications. The circuit supports monochrome micro light-emitting diode (micro-LED) displays with ultrahigh resolution of 7056 pixels per inch (PPI). The circuit is designed and fabricated based on medium-voltage (MV) devices from the 55-nm high-voltage (HV) CMOS process. The total storage capacitance is only 6.588 fF, and the stored charge is susceptible to transistor leakage current, resulting in significant deviations in the average driving currents. To mitigate the deviations, the circuit isolates the switching transistor (TS) from the data signals, increases the body voltage for TS, and minimizes the body area of TS. The low-leakage structure effectively reduces <sc>off</small>-leakage current (IOFF) and reverse-bias p-n-junction leakage current (IREV) of the transistors. Simulation results demonstrate that the proposed circuit produces slight current deviations compared to a conventional 2T1C circuit. Measurement results also confirm that the deviation rate is less than 6.23% for all gray levels (GLs).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"89-92"},"PeriodicalIF":2.0,"publicationDate":"2026-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-16DOI: 10.1109/LSSC.2026.3665218
Geuntae Kim;Hyunjin Ahn;Kyutaek Oh;Ilku Nam;Ockgoo Lee
This letter presents a highly efficient power amplifier (PA) using a parallel-combined vertical multisegment transformer for 5G new radio (NR) applications operating in bands n257 and n258, in a 65-nm bulk CMOS process. A multisegment transformer facilitates a lower provided input impedance than a conventional transformer, enabling the PA to achieve a higher output power. The vertical multisegment transformer also offers lower insertion loss than the conventional transformer, owing to its high coupling factor. In addition, this work demonstrates that utilizing the compact parallel T-line with vertical multisegment transformers, a low-loss characteristic can be achieved by providing an appropriately low input impedance for high output power. To achieve high efficiency in the low-power (LP) region, the PA operates in dual-mode by applying discrete power control. The PA achieves 24.87-dBm saturated output power with 40.27% peak power-added efficiency (PAE) at 27 GHz. Furthermore, it achieves average output powers of 17.6 and 13.8 dBm with average PAEs of 14.02% and 12.31% in the high- and LP modes, respectively, using 800 Msym/s of 5G OFDM using 64-QAM with −25 dB error vector magnitude.
{"title":"Analysis and Design of Power Amplifier Using Parallel-Combined Multisegment Transformer","authors":"Geuntae Kim;Hyunjin Ahn;Kyutaek Oh;Ilku Nam;Ockgoo Lee","doi":"10.1109/LSSC.2026.3665218","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3665218","url":null,"abstract":"This letter presents a highly efficient power amplifier (PA) using a parallel-combined vertical multisegment transformer for 5G new radio (NR) applications operating in bands n257 and n258, in a 65-nm bulk CMOS process. A multisegment transformer facilitates a lower provided input impedance than a conventional transformer, enabling the PA to achieve a higher output power. The vertical multisegment transformer also offers lower insertion loss than the conventional transformer, owing to its high coupling factor. In addition, this work demonstrates that utilizing the compact parallel T-line with vertical multisegment transformers, a low-loss characteristic can be achieved by providing an appropriately low input impedance for high output power. To achieve high efficiency in the low-power (LP) region, the PA operates in dual-mode by applying discrete power control. The PA achieves 24.87-dBm saturated output power with 40.27% peak power-added efficiency (PAE) at 27 GHz. Furthermore, it achieves average output powers of 17.6 and 13.8 dBm with average PAEs of 14.02% and 12.31% in the high- and LP modes, respectively, using 800 Msym/s of 5G OFDM using 64-QAM with −25 dB error vector magnitude.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"85-88"},"PeriodicalIF":2.0,"publicationDate":"2026-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147299525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-13DOI: 10.1109/LSSC.2026.3664504
Sining Pan;Xiaohan Liu;Junlong Zeng;Yihang Cheng;Kofi. A. A. Makinwa;Huaqiang Wu
This letter presents an aging-robust 32-MHz RC frequency reference based on a frequency-locked-loop (FLL). With a temperature compensation scheme that combines BJTs and aging-robust diffusion resistors, the FLL achieves ±1550-ppm inaccuracy from $-40~^{circ }$ C to $125~^{circ }$ C after batch calibration and a low-cost 1-point trim, which increases to ±2350-ppm after accelerated aging. Due to the extensive use of dynamic error-correction techniques, the FLL also achieves a state-of-the-art Allan deviation floor of 0.4 ppm.
{"title":"An Aging-Robust 32-MHz RC Frequency Reference With 0.4-ppm Allan Deviation and ±1550-ppm Inaccuracy From −40 °C to 125 °C After a 1-Point Trim","authors":"Sining Pan;Xiaohan Liu;Junlong Zeng;Yihang Cheng;Kofi. A. A. Makinwa;Huaqiang Wu","doi":"10.1109/LSSC.2026.3664504","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3664504","url":null,"abstract":"This letter presents an aging-robust 32-MHz RC frequency reference based on a frequency-locked-loop (FLL). With a temperature compensation scheme that combines BJTs and aging-robust diffusion resistors, the FLL achieves ±1550-ppm inaccuracy from <inline-formula> <tex-math>$-40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C after batch calibration and a low-cost 1-point trim, which increases to ±2350-ppm after accelerated aging. Due to the extensive use of dynamic error-correction techniques, the FLL also achieves a state-of-the-art Allan deviation floor of 0.4 ppm.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"81-84"},"PeriodicalIF":2.0,"publicationDate":"2026-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-06DOI: 10.1109/LSSC.2026.3661366
Giovanni Scarlato;John R. Long
A two-stage amplifier in 22-nm FD-SOI CMOS integrates a fully-differential bridged T-coil for the first time. Circuit performance is benchmarked against an identical amplifier topology designed with single-ended T-coils (pseudo-differential) and an unpeaked reference. It realizes 70-GHz bandwidth with $12~pm ~2$ -ps group delay and >10-dB return loss across 90 GHz. Bandwidth is 2.2x greater than the unpeaked reference circuit and is 58% larger than a pseudo-differential equivalent. The 54 x $56~mu $ m2 differential T-coil occupies one-third the area of two single-ended coils.
{"title":"A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay","authors":"Giovanni Scarlato;John R. Long","doi":"10.1109/LSSC.2026.3661366","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3661366","url":null,"abstract":"A two-stage amplifier in 22-nm FD-SOI CMOS integrates a fully-differential bridged T-coil for the first time. Circuit performance is benchmarked against an identical amplifier topology designed with single-ended T-coils (pseudo-differential) and an unpeaked reference. It realizes 70-GHz bandwidth with <inline-formula> <tex-math>$12~pm ~2$ </tex-math></inline-formula>-ps group delay and >10-dB return loss across 90 GHz. Bandwidth is 2.2x greater than the unpeaked reference circuit and is 58% larger than a pseudo-differential equivalent. The 54 x <inline-formula> <tex-math>$56~mu $ </tex-math></inline-formula>m2 differential T-coil occupies one-third the area of two single-ended coils.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"65-68"},"PeriodicalIF":2.0,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-06DOI: 10.1109/LSSC.2026.3662477
Zhonghao Chen;Ling-An Cheong;Tianyi Yu;Yiming Chen;Guodong Yin;Teng Yi;Yongpan Liu;Huazhong Yang;Xueqing Li
This letter presents a switched-capacitor SRAM compute-in-memory macro optimized for TinyML inference. Key features include: 1) an area-efficient folded-differential multiply-and-accumulate (FD-MAC) scheme to double the signal margin; 2) a closed-loop floating-inverter amplifier (FIA)-based charge accumulation technique for signal-to-noise ratio enhancement and multiply-and-accumulate (MAC) voltage integration; and 3) a sparsity-aware multistep MAC method to reduce A/D conversions and improve utilization. Fabricated in a 28-nm process, the 32-kb prototype achieves 68.7 TOPS/W energy efficiency and 1.74 TOPS/mm2 area efficiency in 8-bit mode.
{"title":"A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference","authors":"Zhonghao Chen;Ling-An Cheong;Tianyi Yu;Yiming Chen;Guodong Yin;Teng Yi;Yongpan Liu;Huazhong Yang;Xueqing Li","doi":"10.1109/LSSC.2026.3662477","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3662477","url":null,"abstract":"This letter presents a switched-capacitor SRAM compute-in-memory macro optimized for TinyML inference. Key features include: 1) an area-efficient folded-differential multiply-and-accumulate (FD-MAC) scheme to double the signal margin; 2) a closed-loop floating-inverter amplifier (FIA)-based charge accumulation technique for signal-to-noise ratio enhancement and multiply-and-accumulate (MAC) voltage integration; and 3) a sparsity-aware multistep MAC method to reduce A/D conversions and improve utilization. Fabricated in a 28-nm process, the 32-kb prototype achieves 68.7 TOPS/W energy efficiency and 1.74 TOPS/mm2 area efficiency in 8-bit mode.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"73-76"},"PeriodicalIF":2.0,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a novel hardware accelerator compatible with <3-$mu $ m pitch 3-D Cu-Cu hybrid bonding interconnect (HBI) technology, particularly designed to efficiently execute multihead attention (MHA) of encoder transformer models. We present an accelerator that addresses performance losses due to low precision models by incorporating specialized hardware optimizations for quantizer and SoftMax engines. The proposed design features extremely wide SRAM/logic bandwidth for generic matrix multiplication (GEMM) parallelism, including on-the-fly transpose logic and high speed 2-Pass SoftMax, delivering 22.5-GOPS throughput. The Intel 3 prototype with a 3-D footprint of 1.2 mm2 achieves 25 668 Attention/s with no accuracy loss while running I-BERT.
{"title":"A 3-D HBI Compliant 1.536 TB/s/mm2 Bandwidth Scalable Attention Accelerator With 22.5-GOPS Throughput High Speed SoftMax for Quantized Transformers in Intel 3","authors":"Prerna Budhkar;Mirco Sciulli;Srivatsa Rangachar Srinivasa;Gauthaman Murali;Ragh Kuttappa;Paolo Aseron;Trang Nguyen;Vinayak Honkote;Tanay Karnik","doi":"10.1109/LSSC.2026.3659575","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3659575","url":null,"abstract":"This letter presents a novel hardware accelerator compatible with <3-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m pitch 3-D Cu-Cu hybrid bonding interconnect (HBI) technology, particularly designed to efficiently execute multihead attention (MHA) of encoder transformer models. We present an accelerator that addresses performance losses due to low precision models by incorporating specialized hardware optimizations for quantizer and SoftMax engines. The proposed design features extremely wide SRAM/logic bandwidth for generic matrix multiplication (GEMM) parallelism, including on-the-fly transpose logic and high speed 2-Pass SoftMax, delivering 22.5-GOPS throughput. The Intel 3 prototype with a 3-D footprint of 1.2 mm2 achieves 25 668 Attention/s with no accuracy loss while running I-BERT.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"69-72"},"PeriodicalIF":2.0,"publicationDate":"2026-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-20DOI: 10.1109/LSSC.2026.3656180
Yanquan Luo;Mingtao Zhan;Yi Zhong;Nan Sun
This letter presents a power-efficient hybrid ADC architecture: a low-resolution continuous-time (CT) delta-sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback (DCD FB) provides a high jitter-immunity; the quantization of the backend is mainly performed by SAR ADCs, providing a high power efficiency. Capacitor flipping is proposed in the frontend to implement an intrinsically linear 1.5b DCD FB. Nested time-interleaving is proposed in the backend in order to assign the major quantization work to SAR ADCs. Primary–secondary sampling with improved timing is utilized to eliminate timing skew issue while gain more available sampling time and relax backend noise requirement. The ADC is fabricated in 28-nm CMOS process and achieves 70.9-dB SNDR in 300-MHz BW with 39.4-mW power consumption, yielding 169.7-dB Schreier FoM, and the band-edge performance is preserved up to 200 fs, rms clock jitter.
{"title":"A 39.4-mW 300 MHz-BW 70.9 dB-SNDR Hybrid ADC With Resistive Input and 200 fs, rms-Jitter Tolerance","authors":"Yanquan Luo;Mingtao Zhan;Yi Zhong;Nan Sun","doi":"10.1109/LSSC.2026.3656180","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3656180","url":null,"abstract":"This letter presents a power-efficient hybrid ADC architecture: a low-resolution continuous-time (CT) delta-sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback (DCD FB) provides a high jitter-immunity; the quantization of the backend is mainly performed by SAR ADCs, providing a high power efficiency. Capacitor flipping is proposed in the frontend to implement an intrinsically linear 1.5b DCD FB. Nested time-interleaving is proposed in the backend in order to assign the major quantization work to SAR ADCs. Primary–secondary sampling with improved timing is utilized to eliminate timing skew issue while gain more available sampling time and relax backend noise requirement. The ADC is fabricated in 28-nm CMOS process and achieves 70.9-dB SNDR in 300-MHz BW with 39.4-mW power consumption, yielding 169.7-dB Schreier FoM, and the band-edge performance is preserved up to 200 fs, rms clock jitter.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"61-64"},"PeriodicalIF":2.0,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-20DOI: 10.1109/LSSC.2026.3656261
Mohammadreza Zeinali;Sudhakar Pamarti
This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented to demonstrate the concept. The on-chip calibration loop iteratively measures and programs each CTT using short high-voltage pulses until the CTT current matches a reference, achieving device-level current uniformity. Measurement results show an $8times $ reduction in current-source mismatch and linearity improvements to 0.1/0.5 LSB DNL/INL. The proposed approach provides a scalable, low-cost, and nonvolatile solution for analog calibration in deeply scaled CMOS technologies.
{"title":"On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC","authors":"Mohammadreza Zeinali;Sudhakar Pamarti","doi":"10.1109/LSSC.2026.3656261","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3656261","url":null,"abstract":"This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented to demonstrate the concept. The on-chip calibration loop iteratively measures and programs each CTT using short high-voltage pulses until the CTT current matches a reference, achieving device-level current uniformity. Measurement results show an <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> reduction in current-source mismatch and linearity improvements to 0.1/0.5 LSB DNL/INL. The proposed approach provides a scalable, low-cost, and nonvolatile solution for analog calibration in deeply scaled CMOS technologies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"53-56"},"PeriodicalIF":2.0,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-14DOI: 10.1109/LSSC.2026.3654239
Hongyu Lu;Nader Fathy;Patrick P. Mercier
This letter presents a low-jitter digital harmonic-mixing fractional-$N$ phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that would otherwise dominate the in-band jitter, the sinusoidal reference is buffered by a linear source follower, in contrast to the inverters used in other LC-oscillator-based harmonic-mixing PLLs. Implemented in 65 nm CMOS, the proposed PLL achieves 603.8 fs root-mean-square jitter with a 100 MHz integration bandwidth. It occupies $0.12~text {mm}^{2}$ of silicon area and consumes 12.72 mW of power.
{"title":"A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL","authors":"Hongyu Lu;Nader Fathy;Patrick P. Mercier","doi":"10.1109/LSSC.2026.3654239","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3654239","url":null,"abstract":"This letter presents a low-jitter digital harmonic-mixing fractional-<inline-formula> <tex-math>$N$ </tex-math></inline-formula> phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that would otherwise dominate the in-band jitter, the sinusoidal reference is buffered by a linear source follower, in contrast to the inverters used in other LC-oscillator-based harmonic-mixing PLLs. Implemented in 65 nm CMOS, the proposed PLL achieves 603.8 fs root-mean-square jitter with a 100 MHz integration bandwidth. It occupies <inline-formula> <tex-math>$0.12~text {mm}^{2}$ </tex-math></inline-formula> of silicon area and consumes 12.72 mW of power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"57-60"},"PeriodicalIF":2.0,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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