This letter presents an energy-efficient MOS-based temperature sensor, enhanced through transducer and readout circuit integrated design, LSB-first SAR, and energy-efficient comparator. The transducer and readout circuit integrated design reduces noise by combining two blocks into one. With temperature-dependent offset voltage, the comparator integrates with the LSB-first SAR and is optimized for energy efficiency. The LSB-first SAR reduces the number of cycles and energy consumption. In addition, an asynchronous clock controls the circuit, eliminating the need for a timing reference and adjusting speed to temperature to increase measurement robustness. The temperature sensor was fabricated with a 65 nm CMOS process, and the sensor has −60 to $145~^{circ }$ C measurement range. After two-point calibration with a second-order polynomial, errors are −1.93/${+} 1.44~^{circ }$ C over the entire range and −0.96/${+} 0.94~^{circ }$ C from −43 to $137~^{circ }$ C. At room temperature, the sensor achieves 71.8 mK resolution and 41.9 pJ per conversion, resulting in the best resolution figure-of-merit of 216 fJ$cdot $ K2 among MOS-based sensors.
{"title":"A MOS-Based Temperature Sensor With Energy-Efficient Techniques","authors":"Jooeun Kim;Jeongmyeong Kim;Minkyu Yang;Kyounghun Kang;Wanyeong Jung","doi":"10.1109/LSSC.2025.3559900","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3559900","url":null,"abstract":"This letter presents an energy-efficient MOS-based temperature sensor, enhanced through transducer and readout circuit integrated design, LSB-first SAR, and energy-efficient comparator. The transducer and readout circuit integrated design reduces noise by combining two blocks into one. With temperature-dependent offset voltage, the comparator integrates with the LSB-first SAR and is optimized for energy efficiency. The LSB-first SAR reduces the number of cycles and energy consumption. In addition, an asynchronous clock controls the circuit, eliminating the need for a timing reference and adjusting speed to temperature to increase measurement robustness. The temperature sensor was fabricated with a 65 nm CMOS process, and the sensor has −60 to <inline-formula> <tex-math>$145~^{circ }$ </tex-math></inline-formula>C measurement range. After two-point calibration with a second-order polynomial, errors are −1.93/<inline-formula> <tex-math>${+} 1.44~^{circ }$ </tex-math></inline-formula>C over the entire range and −0.96/<inline-formula> <tex-math>${+} 0.94~^{circ }$ </tex-math></inline-formula>C from −43 to <inline-formula> <tex-math>$137~^{circ }$ </tex-math></inline-formula>C. At room temperature, the sensor achieves 71.8 mK resolution and 41.9 pJ per conversion, resulting in the best resolution figure-of-merit of 216 fJ<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>K2 among MOS-based sensors.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"109-112"},"PeriodicalIF":2.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-08DOI: 10.1109/LSSC.2025.3558928
Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He
In computing-in-memory (CIM) architecture, it is necessary to reliably adjust the precision according to the specific demands of the application, enabling a tradeoff between high precision and high energy efficiency. In addition, when performing multibit computations, nonlinearity errors between different bits can adversely affect the network’s accuracy. Therefore, this work proposes an 8Kb dual-edge time-domain CIM macro, which incorporates a segmented precision configuration scheme. By mapping the high and low 4 bits of the 8-bit input to the rising and falling edges of the pulse for independent computation, this design mitigates nonlinearity errors between high and low bits. The precision of multiplication-and-accumulation (MAC) operations for both high and low bits can be independently adjusted, ensuring sufficient accuracy while enhancing energy efficiency. This work attains an energy efficiency ranging from 8.03 to 13.20 TOPS/W in the end. For the CIFAR-10 dataset, when the inputs and weights are of 8-bit precision, this work reaches an inference accuracy of 90.27%–91.92%.
{"title":"A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure","authors":"Chang Xue;Youming Yang;Siyuan He;Gang Du;Yuan Wang;Yandong He","doi":"10.1109/LSSC.2025.3558928","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3558928","url":null,"abstract":"In computing-in-memory (CIM) architecture, it is necessary to reliably adjust the precision according to the specific demands of the application, enabling a tradeoff between high precision and high energy efficiency. In addition, when performing multibit computations, nonlinearity errors between different bits can adversely affect the network’s accuracy. Therefore, this work proposes an 8Kb dual-edge time-domain CIM macro, which incorporates a segmented precision configuration scheme. By mapping the high and low 4 bits of the 8-bit input to the rising and falling edges of the pulse for independent computation, this design mitigates nonlinearity errors between high and low bits. The precision of multiplication-and-accumulation (MAC) operations for both high and low bits can be independently adjusted, ensuring sufficient accuracy while enhancing energy efficiency. This work attains an energy efficiency ranging from 8.03 to 13.20 TOPS/W in the end. For the CIFAR-10 dataset, when the inputs and weights are of 8-bit precision, this work reaches an inference accuracy of 90.27%–91.92%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"117-120"},"PeriodicalIF":2.2,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/LSSC.2025.3557862
Vaishali Choudhary;Pydi Ganga Bahubalindruni
This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a $27~mu $ m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a $V_{mathrm { DD}}$ of 4 V, while consuming only $8~mu $ W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.
{"title":"A Low-Power Fully Dynamic Latched Comparator Using Flexible Oxide TFT Technology","authors":"Vaishali Choudhary;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3557862","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557862","url":null,"abstract":"This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a <inline-formula> <tex-math>$27~mu $ </tex-math></inline-formula>m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a <inline-formula> <tex-math>$V_{mathrm { DD}}$ </tex-math></inline-formula> of 4 V, while consuming only <inline-formula> <tex-math>$8~mu $ </tex-math></inline-formula>W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"101-104"},"PeriodicalIF":2.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143850040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/LSSC.2025.3557524
Mehdi Saberi;Alexandre Schmid
The analysis of the operation of nonlinear circuits, such as voltage level shifters and latched comparators, and therefore the prediction of their propagation delay and power consumption, is challenging. This is because the operating points of the employed nonlinear devices are time-varying. Hence, in this letter, a new approach which uses the trajectory of the operating points of the employed devices is proposed to analyze nonlinear circuits. The proposed method is used to provide a comprehensive study about the operation of the cross-coupled voltage level shifters. The proposed analysis not only formulates the existing contention between the pull-up and pull-down devices but also presents closed-form formulas for the delay as well as the power consumption. Measurement results of a prototype implemented in a standard 0.18-$mu $ m CMOS technology verify the effectiveness of the proposed method.
{"title":"Analysis of Power Consumption and Propagation Delay in Voltage Level Shifters","authors":"Mehdi Saberi;Alexandre Schmid","doi":"10.1109/LSSC.2025.3557524","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557524","url":null,"abstract":"The analysis of the operation of nonlinear circuits, such as voltage level shifters and latched comparators, and therefore the prediction of their propagation delay and power consumption, is challenging. This is because the operating points of the employed nonlinear devices are time-varying. Hence, in this letter, a new approach which uses the trajectory of the operating points of the employed devices is proposed to analyze nonlinear circuits. The proposed method is used to provide a comprehensive study about the operation of the cross-coupled voltage level shifters. The proposed analysis not only formulates the existing contention between the pull-up and pull-down devices but also presents closed-form formulas for the delay as well as the power consumption. Measurement results of a prototype implemented in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS technology verify the effectiveness of the proposed method.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"113-116"},"PeriodicalIF":2.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/LSSC.2025.3557531
Guangxu Shen;Haitao Ma;Chenyang Zhang;Dingyuan Zeng Member;Haoshen Zhu;Wenquan Che
A series of switchable resonators are proposed by incorporating the parasitic effects of two gallium nitride (GaN) high electron mobility transistor (HEMT) devices in this letter, based on which a broadband single-pole double-throw (SPDT) switch is presented with a bandpass response. As for on-chip switches, the ideal transistor is desired to act as a capacitor in its off-state but a resistor in its on-state. In conventional switch designs, the inductive effects of transistors are typically suppressed due to their detrimental impact on impedance matching and isolation. In contrast to this conventional approach, this study proposes a resonator-based design strategy that intentionally exploits and amplifies these inductive characteristics to construct two distinct GaN HEMT-integrated resonators. The first resonator employs the enhanced on-state inductance of a switching transistor combined with an MIM capacitor to form a series resonant network, enabling broadband impedance matching. The second resonator utilizes the large off-state capacitance of a power transistor and a short-circuited transmission line to establish a parallel resonant network. Leveraging the unique properties of these resonators, a broadband switch topology is accordingly proposed and experimentally validated. For demonstration, a SPDT switch is designed and fabricated in a 100 nm GaN-on-Si process. The proposed switch operates from 16 to 33 GHz based on experimental measurements. Two transmission poles are observed in the passband. This result experimentally validates the GaN HEMT-based resonator design.
{"title":"GaN HEMT-Based Resonators Using Parasitic Effects and Its Application to A Ka-band Coupled-Resonator SPDT Switch","authors":"Guangxu Shen;Haitao Ma;Chenyang Zhang;Dingyuan Zeng Member;Haoshen Zhu;Wenquan Che","doi":"10.1109/LSSC.2025.3557531","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3557531","url":null,"abstract":"A series of switchable resonators are proposed by incorporating the parasitic effects of two gallium nitride (GaN) high electron mobility transistor (HEMT) devices in this letter, based on which a broadband single-pole double-throw (SPDT) switch is presented with a bandpass response. As for on-chip switches, the ideal transistor is desired to act as a capacitor in its off-state but a resistor in its on-state. In conventional switch designs, the inductive effects of transistors are typically suppressed due to their detrimental impact on impedance matching and isolation. In contrast to this conventional approach, this study proposes a resonator-based design strategy that intentionally exploits and amplifies these inductive characteristics to construct two distinct GaN HEMT-integrated resonators. The first resonator employs the enhanced on-state inductance of a switching transistor combined with an MIM capacitor to form a series resonant network, enabling broadband impedance matching. The second resonator utilizes the large off-state capacitance of a power transistor and a short-circuited transmission line to establish a parallel resonant network. Leveraging the unique properties of these resonators, a broadband switch topology is accordingly proposed and experimentally validated. For demonstration, a SPDT switch is designed and fabricated in a 100 nm GaN-on-Si process. The proposed switch operates from 16 to 33 GHz based on experimental measurements. Two transmission poles are observed in the passband. This result experimentally validates the GaN HEMT-based resonator design.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"105-108"},"PeriodicalIF":2.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143850828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Frequency-modulated continuous wave (FMCW) LiDAR offers a significant advantage over FMCW RADAR due to its superior lateral resolution, achieving more than a $1000times $ improvement. However, laser nonlinearities require the use of electro-optical phase-locked loops (EO PLLs), and conventional EO PLL-based FMCW LiDAR systems are susceptible to spoofing attacks. To address this vulnerability, this letter introduces an electro-optical (EO) synthesizer designed to generate FMCW signals with randomly varying chirp rates per frame. The synthesizer incorporates an on-chip SRAM-based physically unclonable function (PUF) fabricated in 180-nm RF CMOS, which generates a device-specific random key to enhance the security of FMCW LiDAR against spoofing attacks. The synthesizer supports four programmable chirp rates: from 8.5 to 12 GHz/ms with a chirp period of $600~mu $ s, and from 12.75 to 18 GHz/ms with a chirp period of $200~mu $ s, resulting in a $5times $ increase in generated cloud points compared to existing long-range EO PLL-based FMCW LiDAR systems.
{"title":"Secure FMCW LiDAR Ranging With an Electro-Optical Synthesizer at 5000 Measurements/s","authors":"Marziyeh Rezaei;Liban Hussein;Alana Dee;Shucheng Fang;Qixuan Lin;Mo Li;Sajjad Moazeni","doi":"10.1109/LSSC.2025.3555948","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3555948","url":null,"abstract":"Frequency-modulated continuous wave (FMCW) LiDAR offers a significant advantage over FMCW RADAR due to its superior lateral resolution, achieving more than a <inline-formula> <tex-math>$1000times $ </tex-math></inline-formula> improvement. However, laser nonlinearities require the use of electro-optical phase-locked loops (EO PLLs), and conventional EO PLL-based FMCW LiDAR systems are susceptible to spoofing attacks. To address this vulnerability, this letter introduces an electro-optical (EO) synthesizer designed to generate FMCW signals with randomly varying chirp rates per frame. The synthesizer incorporates an on-chip SRAM-based physically unclonable function (PUF) fabricated in 180-nm RF CMOS, which generates a device-specific random key to enhance the security of FMCW LiDAR against spoofing attacks. The synthesizer supports four programmable chirp rates: from 8.5 to 12 GHz/ms with a chirp period of <inline-formula> <tex-math>$600~mu $ </tex-math></inline-formula>s, and from 12.75 to 18 GHz/ms with a chirp period of <inline-formula> <tex-math>$200~mu $ </tex-math></inline-formula>s, resulting in a <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> increase in generated cloud points compared to existing long-range EO PLL-based FMCW LiDAR systems.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"93-96"},"PeriodicalIF":2.2,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143830476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The proposed low input current ripple (LICR) switched-capacitor (SC) hybrid converter effectively minimizes input current ripple by incorporating a precompensation active biasing electromagnetic interference (EMI) filter (PABEF), addressing EMI issues in automotive applications without requiring large external components. In addition, the current-modulation gate driver (CMGD) helps suppress conducted EMI noise at high frequencies. As a result, the LICR achieves a 74% reduction in input current ripple, EMI noise attenuation of 32 dB at low frequencies and 5 dB at high frequencies, and a peak efficiency of 93.3% at $V_{mathrm { O}}$ /$V_{mathrm { IN}}{=}1.8$ /24.
{"title":"A 24 V-to-1 V Low Input Current Ripple SC Hybrid Converter With Conducted EMI Noise Precompensation Filter and Current-Modulated Gate-Driver for Automobile Application","authors":"Yu-Tse Shih;Li-Jen Huang;Xiao-Quan Wu;Wei-Chieh Hung;Tz-Han Hsu;Kuo-Lin Zheng;Ke-Horng Chen;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai","doi":"10.1109/LSSC.2025.3554811","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3554811","url":null,"abstract":"The proposed low input current ripple (LICR) switched-capacitor (SC) hybrid converter effectively minimizes input current ripple by incorporating a precompensation active biasing electromagnetic interference (EMI) filter (PABEF), addressing EMI issues in automotive applications without requiring large external components. In addition, the current-modulation gate driver (CMGD) helps suppress conducted EMI noise at high frequencies. As a result, the LICR achieves a 74% reduction in input current ripple, EMI noise attenuation of 32 dB at low frequencies and 5 dB at high frequencies, and a peak efficiency of 93.3% at <inline-formula> <tex-math>$V_{mathrm { O}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$V_{mathrm { IN}}{=}1.8$ </tex-math></inline-formula>/24.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"89-92"},"PeriodicalIF":2.2,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/LSSC.2025.3552520
Zehang Wu;Chi-Hang Chan;Yan Zhu;Rui P. Martins;Minglei Zhang
This letter presents a 32-GS/s per-way hierarchical sampling front-end (SFE) for time-interleaved ADCs, featuring both high linearity and energy efficiency with inherent embedded gain from an inverter-based topology. The P/N ratio configuration extends its applicable input common-mode voltage range. Both active and passive extensions improve the bandwidth of the SFE supplied by a core-device voltage. Furthermore, an improved dual-path bootstrapped switch enhances the sampling bandwidth and linearity at 8 GS/s. Fabricated in a 28-nm CMOS process, the inverter-based SFE achieves 30-GHz bandwidth while consuming 49.4 mW from a 0.95-V supply. The measured spurious free dynamic range (SFDR) and signal-to-noise and -distortion ratio (SNDR) at 50-GHz input are 46.9 dB and 36.1 dB, respectively.
{"title":"An Inverter-Based Sampling Front-End Achieving >46-dB SFDR at 50-GHz Input","authors":"Zehang Wu;Chi-Hang Chan;Yan Zhu;Rui P. Martins;Minglei Zhang","doi":"10.1109/LSSC.2025.3552520","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3552520","url":null,"abstract":"This letter presents a 32-GS/s per-way hierarchical sampling front-end (SFE) for time-interleaved ADCs, featuring both high linearity and energy efficiency with inherent embedded gain from an inverter-based topology. The P/N ratio configuration extends its applicable input common-mode voltage range. Both active and passive extensions improve the bandwidth of the SFE supplied by a core-device voltage. Furthermore, an improved dual-path bootstrapped switch enhances the sampling bandwidth and linearity at 8 GS/s. Fabricated in a 28-nm CMOS process, the inverter-based SFE achieves 30-GHz bandwidth while consuming 49.4 mW from a 0.95-V supply. The measured spurious free dynamic range (SFDR) and signal-to-noise and -distortion ratio (SNDR) at 50-GHz input are 46.9 dB and 36.1 dB, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"81-84"},"PeriodicalIF":2.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/LSSC.2025.3551357
Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong
This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-$mu $ m CMOS process.
{"title":"Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure","authors":"Young-Ju Oh;Hyun-Woo Jeong;Hyeonho Park;Jeeyoung Shin;Junwon Jeong;Woong Choi;Sung-Wan Hong","doi":"10.1109/LSSC.2025.3551357","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3551357","url":null,"abstract":"This letter presents a compact single-stage buffer amplifier designed to drive a wide range of capacitive loads (CL). To further reduce power consumption and silicon area compared to previous single-stage rail-to-rail amplifiers, this letter proposes an asymmetric rail-to-rail class AB output structure. To achieve a high slew rate, the proposed amplifier employs positive feedback loops and a dynamic floating node. A prototype chip successfully drove a wide range of CL, from 250 pF to 15 nF, while achieving a fast transient response. The chip was fabricated using a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"73-76"},"PeriodicalIF":2.2,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a global resonant clocking mesh architecture utilizing backside metal layers in an 18A class technology. Rotary traveling wave oscillators are implemented to provide synchronous low-skew, low-jitter, and 50% duty cycle clocks across a graphics core. To provide dynamic frequency and voltage scaling capabilities across a wide range of operating conditions, a high-speed fractional divider is designed. The proposed architecture is implemented on a 1.6 mm $times $ 1.6 mm graphics core achieving FoMJ of 246 dB FoMT 190.3dBc/Hz.
{"title":"A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology","authors":"Ragh Kuttappa;Vinayak Honkote;Amreesh Rao;Gaurav Kamalkar;Kailash Chandrashekar;Eric Finley;Chaitanya Sankuratri;Faran Rafiq;Robert Orton;Nils Hernandez;Anuradha Srinivasan;Tanay Karnik","doi":"10.1109/LSSC.2025.3552251","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3552251","url":null,"abstract":"This letter presents a global resonant clocking mesh architecture utilizing backside metal layers in an 18A class technology. Rotary traveling wave oscillators are implemented to provide synchronous low-skew, low-jitter, and 50% duty cycle clocks across a graphics core. To provide dynamic frequency and voltage scaling capabilities across a wide range of operating conditions, a high-speed fractional divider is designed. The proposed architecture is implemented on a 1.6 mm <inline-formula> <tex-math>$times $ </tex-math></inline-formula> 1.6 mm graphics core achieving FoMJ of 246 dB FoMT 190.3dBc/Hz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"85-88"},"PeriodicalIF":2.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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