For solving various social issues, sensing technology has gained significant interest. Terahertz waves, which combine the high resolution of light and transparency of radio waves, enable visualization of obstacles behind internal structures. So, it offers potential for new solutions. This letter introduces the overview of a short-distance sensing system based on the full digital MIMO radar concept, the design, and fundamental evaluation results of 300 GHz RFIC using CMOS technology, as well as the achievements of imaging using 300 GHz terahertz wave based on actual measurements. Since the terahertz band can obtain an ultrawideband spectrum, several millimeter resolution imaging can be performed in azimuth, elevation, and depth direction. We show the feasibility of the security gate application with the measured high-resolution tomographic images.
{"title":"Terahertz Sensing With CMOS-RFIC:Feasibility Verification for Short-Range Imaging Using 300-GHz MIMO Radar","authors":"Ichiro Somada;Akihito Hirai;Akinori Taira;Keigo Nakatani;Kazuaki Ishioka;Takuma Nishimura;Koji Yamanaka","doi":"10.1109/LSSC.2024.3490547","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3490547","url":null,"abstract":"For solving various social issues, sensing technology has gained significant interest. Terahertz waves, which combine the high resolution of light and transparency of radio waves, enable visualization of obstacles behind internal structures. So, it offers potential for new solutions. This letter introduces the overview of a short-distance sensing system based on the full digital MIMO radar concept, the design, and fundamental evaluation results of 300 GHz RFIC using CMOS technology, as well as the achievements of imaging using 300 GHz terahertz wave based on actual measurements. Since the terahertz band can obtain an ultrawideband spectrum, several millimeter resolution imaging can be performed in azimuth, elevation, and depth direction. We show the feasibility of the security gate application with the measured high-resolution tomographic images.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"343-346"},"PeriodicalIF":2.2,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142671119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/LSSC.2024.3488001
Lei Lei;Zhiming Chen
This letter proposes a $C/g_{m}$ method for analyzing the peak frequency shift caused by parasitic parameters in gain-boosted N-path switched-capacitor bandpass filter (GB-BPF). This method eliminates the device width variable, addressing the interdependencies among various parameters in GB-BPF. Numerical solution for peak frequency shift is obtained, and the impact of each variable on frequency shift is accurately quantified. Using the proposed $C/g_{m}$ variable, the optimal bias voltage is determined to minimize the peak frequency shift for same parasitic parameters. Additionally, optimization strategies for adjusting the filter capacitance and switching frequency are proposed. Finally, a GB-BPF is implemented in a 90-nm CMOS process. The accuracy of the analysis is verified by comparing the measured and simulated results with the theoretically derived results.
{"title":"Analysis and Optimization of Parasitics-Induced Peak Frequency Shift in Gain-Boosted N-Path Switched-Capacitor Bandpass Filter","authors":"Lei Lei;Zhiming Chen","doi":"10.1109/LSSC.2024.3488001","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3488001","url":null,"abstract":"This letter proposes a \u0000<inline-formula> <tex-math>$C/g_{m}$ </tex-math></inline-formula>\u0000 method for analyzing the peak frequency shift caused by parasitic parameters in gain-boosted N-path switched-capacitor bandpass filter (GB-BPF). This method eliminates the device width variable, addressing the interdependencies among various parameters in GB-BPF. Numerical solution for peak frequency shift is obtained, and the impact of each variable on frequency shift is accurately quantified. Using the proposed \u0000<inline-formula> <tex-math>$C/g_{m}$ </tex-math></inline-formula>\u0000 variable, the optimal bias voltage is determined to minimize the peak frequency shift for same parasitic parameters. Additionally, optimization strategies for adjusting the filter capacitance and switching frequency are proposed. Finally, a GB-BPF is implemented in a 90-nm CMOS process. The accuracy of the analysis is verified by comparing the measured and simulated results with the theoretically derived results.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"339-342"},"PeriodicalIF":2.2,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-29DOI: 10.1109/LSSC.2024.3487586
Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang
In this letter, a 28-GHz variable-gain phase shifter (VG-PS) with phase compensation designed using a Gilbert-cell-based vector summation amplifier integrated with a current-type digital-to-analog converter (DAC) and a quadrature all-pass filter (QAF) I/Q generator, fabricated using the 90-nm CMOS process. The VG-PS achieves a 360° phase-shifting range with a 7-bit resolution and 7-dB gain-tuning range. The vector summation amplifier synthesizes a vector by combining in-phase and quadrature-phase signals, which are determined by the tail currents of the vector summation amplifier. Tail currents for the vector summation amplifier are generated and mirrored by the current-type DAC. Any mismatch between the DAC’s tail current and that of the vector summation amplifier results in amplitude and phase discrepancies in the synthesized vector. The proposed calibration method optimizes amplitude and phase accuracy through current addition and subtraction, eliminating the need for I/Q calibration of the QAF. Measurements show root-mean-square gain and phase errors of the VG-PS at 28 GHz to be 0.12 dB and 0.23°, respectively. The chip size of VG-PS is 0.723 mm2, including pads, and it consumes 32 mW at maximum gain state.
{"title":"A 28-GHz Variable-Gain Phase Shifter With Phase Compensation Using Analog Addition and Subtraction Method","authors":"Hsing-Hung Lin;Chung-Ping Chen;Yu-Teng Chang","doi":"10.1109/LSSC.2024.3487586","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3487586","url":null,"abstract":"In this letter, a 28-GHz variable-gain phase shifter (VG-PS) with phase compensation designed using a Gilbert-cell-based vector summation amplifier integrated with a current-type digital-to-analog converter (DAC) and a quadrature all-pass filter (QAF) I/Q generator, fabricated using the 90-nm CMOS process. The VG-PS achieves a 360° phase-shifting range with a 7-bit resolution and 7-dB gain-tuning range. The vector summation amplifier synthesizes a vector by combining in-phase and quadrature-phase signals, which are determined by the tail currents of the vector summation amplifier. Tail currents for the vector summation amplifier are generated and mirrored by the current-type DAC. Any mismatch between the DAC’s tail current and that of the vector summation amplifier results in amplitude and phase discrepancies in the synthesized vector. The proposed calibration method optimizes amplitude and phase accuracy through current addition and subtraction, eliminating the need for I/Q calibration of the QAF. Measurements show root-mean-square gain and phase errors of the VG-PS at 28 GHz to be 0.12 dB and 0.23°, respectively. The chip size of VG-PS is 0.723 mm2, including pads, and it consumes 32 mW at maximum gain state.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"335-338"},"PeriodicalIF":2.2,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142636474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-24DOI: 10.1109/LSSC.2024.3486234
Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim
We introduce a high-throughput reconfigurable forward error correction (FEC) decoder capable of decoding BCH, RS, and open FEC (oFEC) codes. With a reconfigurable BCH inner code, the proposed decoder in the oFEC mode provides a wide range of coding gain and throughput to enable efficient and reliable intersatellite optical communication. It features unprecedented reconfigurability for BCH/RS codes in terms of Galois field (GF) size, code length, code rate, and parallel factor, providing tradeoffs between error correction performance, energy, and throughput. Fabricated in 12-nm CMOS technology, the decoder achieves a throughput of 33.06 Gb/s, energy efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at $10^{text {-6}}$ BER with an oFEC code using inner BCH(256, 223).
{"title":"A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication","authors":"Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim","doi":"10.1109/LSSC.2024.3486234","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3486234","url":null,"abstract":"We introduce a high-throughput reconfigurable forward error correction (FEC) decoder capable of decoding BCH, RS, and open FEC (oFEC) codes. With a reconfigurable BCH inner code, the proposed decoder in the oFEC mode provides a wide range of coding gain and throughput to enable efficient and reliable intersatellite optical communication. It features unprecedented reconfigurability for BCH/RS codes in terms of Galois field (GF) size, code length, code rate, and parallel factor, providing tradeoffs between error correction performance, energy, and throughput. Fabricated in 12-nm CMOS technology, the decoder achieves a throughput of 33.06 Gb/s, energy efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at \u0000<inline-formula> <tex-math>$10^{text {-6}}$ </tex-math></inline-formula>\u0000 BER with an oFEC code using inner BCH(256, 223).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"331-334"},"PeriodicalIF":2.2,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-11DOI: 10.1109/LSSC.2024.3478837
Petar Barac;Matthew Bajor;Peter R. Kinget
A time-modulated LO (TM-LO) vector modulator (VM) architecture using a time domain approach for amplitude scaling and phase shifting received signals is presented. The TM-LO uses rail-to-rail LO waveforms generated from digitally synthesized blocks and pass-gate switches to perform the amplitude/phase control. A single element receiver achieves 0.2 dB RMS gain error and 1.4° RMS phase error with 5 bits of amplitude/phase resolution across a 360° range is implemented in a 65 nm CMOS process. Without time-modulation, the hardware is capable of 3-bits of resolution. The inherent digital nature of TM-LO architecture provides opportunity very compact front-ends suitable for large arrays and lower voltage technologies. Four TM-LO chips were used to create a beamforming receiver
{"title":"Time-Modulated-LO-Path Vector Modulators for Beamforming Receivers","authors":"Petar Barac;Matthew Bajor;Peter R. Kinget","doi":"10.1109/LSSC.2024.3478837","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3478837","url":null,"abstract":"A time-modulated LO (TM-LO) vector modulator (VM) architecture using a time domain approach for amplitude scaling and phase shifting received signals is presented. The TM-LO uses rail-to-rail LO waveforms generated from digitally synthesized blocks and pass-gate switches to perform the amplitude/phase control. A single element receiver achieves 0.2 dB RMS gain error and 1.4° RMS phase error with 5 bits of amplitude/phase resolution across a 360° range is implemented in a 65 nm CMOS process. Without time-modulation, the hardware is capable of 3-bits of resolution. The inherent digital nature of TM-LO architecture provides opportunity very compact front-ends suitable for large arrays and lower voltage technologies. Four TM-LO chips were used to create a beamforming receiver","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"323-326"},"PeriodicalIF":2.2,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast-locking low-jitter hybrid frequency synthesizer using a charge-pump phase-locked loop (CP-PLL) and a multiplying delay-locked loop (MDLL) is presented. The CP-PLL uses a discriminator-aided detector (DAD) to alleviate the cycle-slipping issue and an auto-zero phase error compensator (AZ-PEC) to compensate the accumulated phase error during frequency acquisition to enhance the settling time. Then, the MDLL overcomes the jitter accumulation of CP-PLL. The synthesizer was fabricated in a 90-nm CMOS process. The output frequency ranges from 1 to 3 GHz. When switching from 1 to 2.5 GHz, the measured settling time using DAD and AZ-PEC is 520 ns, which is approximately 26 reference clock cycles. The power consumption is 12 mW at 2.5 GHz for a supply of 1.2 V. The integral root-mean-square jitter over 1 kHz–100 MHz is 1.62 ps.
{"title":"A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation","authors":"Ching-Yuan Yang;Hao-Cheng Hsu;Ping-Heng Wu;Samuel Palermo","doi":"10.1109/LSSC.2024.3478799","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3478799","url":null,"abstract":"A fast-locking low-jitter hybrid frequency synthesizer using a charge-pump phase-locked loop (CP-PLL) and a multiplying delay-locked loop (MDLL) is presented. The CP-PLL uses a discriminator-aided detector (DAD) to alleviate the cycle-slipping issue and an auto-zero phase error compensator (AZ-PEC) to compensate the accumulated phase error during frequency acquisition to enhance the settling time. Then, the MDLL overcomes the jitter accumulation of CP-PLL. The synthesizer was fabricated in a 90-nm CMOS process. The output frequency ranges from 1 to 3 GHz. When switching from 1 to 2.5 GHz, the measured settling time using DAD and AZ-PEC is 520 ns, which is approximately 26 reference clock cycles. The power consumption is 12 mW at 2.5 GHz for a supply of 1.2 V. The integral root-mean-square jitter over 1 kHz–100 MHz is 1.62 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"315-318"},"PeriodicalIF":2.2,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1109/LSSC.2024.3477619
Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao
A digital SRAM-based computing-in-memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. A new 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves $6.9times $ in energy at 1.2 V and $2.33times $ in area compared with the conventional statistics counters in a 55-nm CMOS technology.
{"title":"A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management","authors":"Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao","doi":"10.1109/LSSC.2024.3477619","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3477619","url":null,"abstract":"A digital SRAM-based computing-in-memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. A new 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves \u0000<inline-formula> <tex-math>$6.9times $ </tex-math></inline-formula>\u0000 in energy at 1.2 V and \u0000<inline-formula> <tex-math>$2.33times $ </tex-math></inline-formula>\u0000 in area compared with the conventional statistics counters in a 55-nm CMOS technology.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"327-330"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142587641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a 20-Gb/s/pin single-ended pulse amplitude modulation (PAM)-4 transceiver implemented in an 8-nm CMOS process, featuring an advanced switching jitter compensation (SWJC) technique and a DQS-driven amplifier bias generation method for a source-synchronous clocking system, aimed for next-generation low-power memory interfaces utilizing multilevel signaling. The proposed prechannel SWJC (pre-SWJC) in the transmitter adjusts the input edge timing of the thermometer PAM-4 driver to control the transitions of the PAM-4 signal. This transition control advances the outermost transitions, thereby not only minimizing the switching jitter (SWJ) of the middle eye but also enhancing the effectiveness of the post-channel SWJC (post-SWJC) performed at the receiver. Ultimately, the comprehensive solution combining the proposed pre/post-SWJC improved the timing margin from 0.26 UI to 0.39 UI at a BER of 1e-12, with only a 4.5% increase in power consumption and a 0.59% area overhead. Additionally, the proposed DQS-driven biasing technique in the receiver supplies biases for the amplifiers in the data lanes by utilizing the common-mode feedback of the replica amplifier in the differential clock lane. This approach reduces variation sources compared to the self-biasing structure that uses common-mode feedback in the data lanes, thereby improving the standard deviation of the amplifier’s bias voltage and gain variation by 58.3%.
{"title":"An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver With Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing","authors":"Kyunghwan Min;Jahoon Jin;Soo-Min Lee;Sodam Ju;Jisu Yook;Jihoon Lee;Yunji Hong;Sung-Sik Park;Sang-Ho Kim;Jongwoo Lee;Hyungjong Ko","doi":"10.1109/LSSC.2024.3477736","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3477736","url":null,"abstract":"This letter presents a 20-Gb/s/pin single-ended pulse amplitude modulation (PAM)-4 transceiver implemented in an 8-nm CMOS process, featuring an advanced switching jitter compensation (SWJC) technique and a DQS-driven amplifier bias generation method for a source-synchronous clocking system, aimed for next-generation low-power memory interfaces utilizing multilevel signaling. The proposed prechannel SWJC (pre-SWJC) in the transmitter adjusts the input edge timing of the thermometer PAM-4 driver to control the transitions of the PAM-4 signal. This transition control advances the outermost transitions, thereby not only minimizing the switching jitter (SWJ) of the middle eye but also enhancing the effectiveness of the post-channel SWJC (post-SWJC) performed at the receiver. Ultimately, the comprehensive solution combining the proposed pre/post-SWJC improved the timing margin from 0.26 UI to 0.39 UI at a BER of 1e-12, with only a 4.5% increase in power consumption and a 0.59% area overhead. Additionally, the proposed DQS-driven biasing technique in the receiver supplies biases for the amplifiers in the data lanes by utilizing the common-mode feedback of the replica amplifier in the differential clock lane. This approach reduces variation sources compared to the self-biasing structure that uses common-mode feedback in the data lanes, thereby improving the standard deviation of the amplifier’s bias voltage and gain variation by 58.3%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"319-322"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-08DOI: 10.1109/LSSC.2024.3476194
Marco Privitera;Alfio Dario Grasso;Andrea Ballo;Massimo Alioto
A four-stage operational transconductance amplifier (OTA) for ultralow-power applications is introduced in this letter. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the traditionally difficult compensation of four-stage OTAs and bringing it back to the simplicity of three-stage OTAs. At the same time, the proposed circuit achieves high power efficiency, as evidenced by the > $3.7times $ (> $11.3times $ ) improvement in the large-signal (small-signal) power efficiency figure of merit ${mathrm { FOM}}_{L}~({mathrm { FOM}}_{S})$ , compared to prior four-stage OTAs (sub-1 V multistage OTAs). Thanks to the lower sensitivity of the phase margin to the load capacitance, the proposed OTA remains stable under a wide range of loads (double-sided as in any three- and four-stage OTA), achieving a max/min ratio of the load capacitance of > $100times $ .
本信介绍了一种用于超低功耗应用的四级运算跨导放大器（OTA）。所提出的电路包括频率补偿，只需最少的晶体管数量和无源器件，克服了四级 OTA 传统上难以补偿的问题，使其回归到三级 OTA 的简单性。同时，与之前的四级 OTA（1 V 以下的多级 OTA）相比，所提出的电路实现了较高的功率效率，其大信号（小信号）功率效率优值 ${mathrm { FOM}}_{L}~({mathrm { FOM}}_{S})$ 提高了 > 3.7 （> $11.3）倍。由于相位裕度对负载电容的敏感性较低，因此所提出的 OTA 在各种负载（与任何三级和四级 OTA 一样为双面负载）下都能保持稳定，负载电容的最大/最小比> $100times $。
{"title":"0.6-V, μW-Power Four-Stage OTA With Minimal Components, and 100× Load Range","authors":"Marco Privitera;Alfio Dario Grasso;Andrea Ballo;Massimo Alioto","doi":"10.1109/LSSC.2024.3476194","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3476194","url":null,"abstract":"A four-stage operational transconductance amplifier (OTA) for ultralow-power applications is introduced in this letter. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the traditionally difficult compensation of four-stage OTAs and bringing it back to the simplicity of three-stage OTAs. At the same time, the proposed circuit achieves high power efficiency, as evidenced by the >\u0000<inline-formula> <tex-math>$3.7times $ </tex-math></inline-formula>\u0000 (>\u0000<inline-formula> <tex-math>$11.3times $ </tex-math></inline-formula>\u0000) improvement in the large-signal (small-signal) power efficiency figure of merit \u0000<inline-formula> <tex-math>${mathrm { FOM}}_{L}~({mathrm { FOM}}_{S})$ </tex-math></inline-formula>\u0000, compared to prior four-stage OTAs (sub-1 V multistage OTAs). Thanks to the lower sensitivity of the phase margin to the load capacitance, the proposed OTA remains stable under a wide range of loads (double-sided as in any three- and four-stage OTA), achieving a max/min ratio of the load capacitance of >\u0000<inline-formula> <tex-math>$100times $ </tex-math></inline-formula>\u0000.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"311-314"},"PeriodicalIF":2.2,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, a broadband gallium nitride (GaN) monolithic microwave integrated circuit Doherty power amplifier (DPA) using a compact short-circuited coupler (CSC) is presented. To enhance the bandwidth and reduce the size of integrated DPA, the conventional $lambda $ /2 transmission line in the peaking output matching network is replaced by the CSC structure. Detailed theoretical analysis and design procedures are provided. Based on the proposed solution, a 5.1–7.2-GHz DPA is designed using a 0.12- $mu $ m GaN HEMT process. The fractional bandwidth (FBW) is 34.1%. The measurement results show a saturated output power of 37.2–39 dBm and a 6-dB back-off drain efficiency of 38.4%–50.5% across the design bands with a chip size of $2.6times 2$ .6 mm. The adjacent channel power ratio (ACPR) under 100-MHz single-carrier 64 QAM modulation signal with a 6-dB peak-to-average power ratio (PAPR) excitation is better than −45 dBc with digital predistortion (DPD).
{"title":"Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler","authors":"Shun Wan;Wenhua Chen;Guansheng Lv;Yuhang Zhang;Xu Shi;Zhenghe Feng","doi":"10.1109/LSSC.2024.3471855","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3471855","url":null,"abstract":"In this letter, a broadband gallium nitride (GaN) monolithic microwave integrated circuit Doherty power amplifier (DPA) using a compact short-circuited coupler (CSC) is presented. To enhance the bandwidth and reduce the size of integrated DPA, the conventional \u0000<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>\u0000/2 transmission line in the peaking output matching network is replaced by the CSC structure. Detailed theoretical analysis and design procedures are provided. Based on the proposed solution, a 5.1–7.2-GHz DPA is designed using a 0.12-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m GaN HEMT process. The fractional bandwidth (FBW) is 34.1%. The measurement results show a saturated output power of 37.2–39 dBm and a 6-dB back-off drain efficiency of 38.4%–50.5% across the design bands with a chip size of \u0000<inline-formula> <tex-math>$2.6times 2$ </tex-math></inline-formula>\u0000.6 mm. The adjacent channel power ratio (ACPR) under 100-MHz single-carrier 64 QAM modulation signal with a 6-dB peak-to-average power ratio (PAPR) excitation is better than −45 dBc with digital predistortion (DPD).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"307-310"},"PeriodicalIF":2.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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