Pub Date : 2025-02-05DOI: 10.1109/LSSC.2025.3539228
Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad
This work represents a 140 GHz wideband 2-D scalable phased array in 28-nm bulk CMOS technology. The chip integrates $2times 2$ transceiving elements with on-chip antennas and a $times 16$ LO multiplication chain in $2.115times 2$ .115 mm2. The elements are forming an RF beamformer while keeping approximately half-wavelength spacing between the elements. The integrated antennas leverage substrate thinning and substrate mode cancellation to boost the array radiation efficiency. The system adopts a superheterodyne transceiver (TRX) architecture with 25 GHz IF center frequency. The proposed work achieves 1.54 pJ/b and 80 Gb/s over-the-air (OTA) using 16-QAM modulation scheme for the overall transmit-receive link. To the best of the authors’ knowledge, this work achieves the highest reported array-level OTA data rate while improving the energy efficiency (pJ/b) by approximately an order of magnitude compared to other D-band transceiver arrays.
{"title":"A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS","authors":"Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3539228","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3539228","url":null,"abstract":"This work represents a 140 GHz wideband 2-D scalable phased array in 28-nm bulk CMOS technology. The chip integrates <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> transceiving elements with on-chip antennas and a <inline-formula> <tex-math>$times 16$ </tex-math></inline-formula> LO multiplication chain in <inline-formula> <tex-math>$2.115times 2$ </tex-math></inline-formula>.115 mm2. The elements are forming an RF beamformer while keeping approximately half-wavelength spacing between the elements. The integrated antennas leverage substrate thinning and substrate mode cancellation to boost the array radiation efficiency. The system adopts a superheterodyne transceiver (TRX) architecture with 25 GHz IF center frequency. The proposed work achieves 1.54 pJ/b and 80 Gb/s over-the-air (OTA) using 16-QAM modulation scheme for the overall transmit-receive link. To the best of the authors’ knowledge, this work achieves the highest reported array-level OTA data rate while improving the energy efficiency (pJ/b) by approximately an order of magnitude compared to other D-band transceiver arrays.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"61-64"},"PeriodicalIF":2.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents a low-noise, power-efficient, and pulsatile-interference stabilized photocurrent readout circuit for under-display ambient light sensors (ALS). To achieve pA-level input noise and seven decades of input current dynamic range (DR) simultaneously, a logarithmic transimpedance amplifier (TIA) with a diode-connected MOS feedback is set as the first stage of the ALS. An auto-tracking zero, implemented in the amplifier of the TIA, improves the phase-margin and reduces the settling time against pulsatile interference without extra power consumption. The TIA output is then quantized by a first-order 9-bit incremental delta-sigma modulator. Fabricated in a standard 0.18-$mu $ m CMOS process, the proposed ALS achieves the best-in-the-class input-referred current noise of $0.6~rm {pA}_{mathrm {rms}}$ within a 400-$mu $ s readout time. The total input range of $1.7~rm {pA}_{mathrm {PP}}$ –$5~mu rm {A}_{mathrm {PP}}$ corresponds to a DR of 129 dB while consuming 0.86 mW at a 1.8-V supply.
{"title":"A 0.86 mW 17 fA/√Hz, 129-dB DR Current-Sensing Front-End for Under-Display Ambient Light Sensor With Zero-Compensated Logarithmic TIA","authors":"Liheng Liu;Tianxiang Qu;Hao Li;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3528962","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528962","url":null,"abstract":"This letter presents a low-noise, power-efficient, and pulsatile-interference stabilized photocurrent readout circuit for under-display ambient light sensors (ALS). To achieve pA-level input noise and seven decades of input current dynamic range (DR) simultaneously, a logarithmic transimpedance amplifier (TIA) with a diode-connected MOS feedback is set as the first stage of the ALS. An auto-tracking zero, implemented in the amplifier of the TIA, improves the phase-margin and reduces the settling time against pulsatile interference without extra power consumption. The TIA output is then quantized by a first-order 9-bit incremental delta-sigma modulator. Fabricated in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, the proposed ALS achieves the best-in-the-class input-referred current noise of <inline-formula> <tex-math>$0.6~rm {pA}_{mathrm {rms}}$ </tex-math></inline-formula> within a 400-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s readout time. The total input range of <inline-formula> <tex-math>$1.7~rm {pA}_{mathrm {PP}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$5~mu rm {A}_{mathrm {PP}}$ </tex-math></inline-formula> corresponds to a DR of 129 dB while consuming 0.86 mW at a 1.8-V supply.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"49-52"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-13DOI: 10.1109/LSSC.2025.3529347
Jin-Fa Chang
We demonstrate a four-way wide-band power amplifier (PA1) with a 1:2 capacitance-ratio-equivalent power combiner (PC) and a dynamic-threshold-voltage MOSFET with a resistor (DTMOS-R) using a 90-nm CMOS. Another PA (PA2) without a DTMOS-R using low-loss micro-strip line inductors replaced with a PC is demonstrated for contrast. A low-loss PC is realized using equal $lambda $ /4 spiral transmission line inductors based on a $lambda $ /9 one (with a 1:2 capacitance ratio involving Cp1 and Cp2) for low-loss output-stage matching. The output power of the output stage of PA1, with low-threshold voltage ($V_{mathrm { th}}$ ) due to the DTMOS-R and low Rds based on the parallel four-way output, is enhanced using a PC. Between 20–26 GHz, PA1 achieves a prominent S21 of 23.2 dB, peak power-added-efficiency (PAE) between 20.8%–29.7%, and saturation output power between 19.9–21.2 dBm. Moreover, the output 1-dB compression point (OP1dB) is 16–20.4 dBm between 20–26 GHz. Using the PC and DTMOS-R yields the bulk CMOS PA’s high performance (Pout, PAE, and OP1dB), comparable to recent state-of-the-art millimeter-wave PAs, i.e., SOI/SiGe processes.
{"title":"20–26-GHz CMOS PA With High Pout and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner","authors":"Jin-Fa Chang","doi":"10.1109/LSSC.2025.3529347","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3529347","url":null,"abstract":"We demonstrate a four-way wide-band power amplifier (PA1) with a 1:2 capacitance-ratio-equivalent power combiner (PC) and a dynamic-threshold-voltage MOSFET with a resistor (DTMOS-R) using a 90-nm CMOS. Another PA (PA2) without a DTMOS-R using low-loss micro-strip line inductors replaced with a PC is demonstrated for contrast. A low-loss PC is realized using equal <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/4 spiral transmission line inductors based on a <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/9 one (with a 1:2 capacitance ratio involving Cp1 and Cp2) for low-loss output-stage matching. The output power of the output stage of PA1, with low-threshold voltage (<inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>) due to the DTMOS-R and low Rds based on the parallel four-way output, is enhanced using a PC. Between 20–26 GHz, PA1 achieves a prominent S21 of 23.2 dB, peak power-added-efficiency (PAE) between 20.8%–29.7%, and saturation output power between 19.9–21.2 dBm. Moreover, the output 1-dB compression point (OP1dB) is 16–20.4 dBm between 20–26 GHz. Using the PC and DTMOS-R yields the bulk CMOS PA’s high performance (Pout, PAE, and OP1dB), comparable to recent state-of-the-art millimeter-wave PAs, i.e., SOI/SiGe processes.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"53-56"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-10DOI: 10.1109/LSSC.2025.3528055
Yahia Ibrahim;Ali Niknejad
This letter presents a compact Doherty power amplifier (PA) featuring a single transformer balun. A novel envelope power detector architecture is introduced for high-bandwidth (BW) adaptive biasing, that is, insensitive to process-voltage–temperature (PVT) variations. The measured PA attains a saturated power $(mathbf {P_{mathrm { sat}}})$ exceeding 20.2 dBm and a power gain of 19.5 dB across the frequency range of 23–28 GHz. Moreover, it exhibits a peak power added efficiency (PAE) of 38% and a 6-dB power back-off (PBO) PAE of 27% at 25 GHz. The proposed adaptive biasing scheme enables a modulation BW of up to 800 MHz for a 64-QAM signal. Under this setting, the average output power $(mathbf {P_{avg}})$ is measured at 11.3 dBm with an RMS error vector magnitude (EVM) of −24.5 dB and an average PAE of 15.5%. The PA is fabricated in Global Foundries 45-nm-SOI technology with a compact area of 0.27 mm2. To the best of the authors’ knowledge, this work is the first to demonstrate robust performance for Doherty PAs across PVT variations.
{"title":"A 23–28-GHz Doherty Power Amplifier With a PVT Insensitive Power Detection for Adaptive Biasing","authors":"Yahia Ibrahim;Ali Niknejad","doi":"10.1109/LSSC.2025.3528055","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528055","url":null,"abstract":"This letter presents a compact Doherty power amplifier (PA) featuring a single transformer balun. A novel envelope power detector architecture is introduced for high-bandwidth (BW) adaptive biasing, that is, insensitive to process-voltage–temperature (PVT) variations. The measured PA attains a saturated power <inline-formula> <tex-math>$(mathbf {P_{mathrm { sat}}})$ </tex-math></inline-formula> exceeding 20.2 dBm and a power gain of 19.5 dB across the frequency range of 23–28 GHz. Moreover, it exhibits a peak power added efficiency (PAE) of 38% and a 6-dB power back-off (PBO) PAE of 27% at 25 GHz. The proposed adaptive biasing scheme enables a modulation BW of up to 800 MHz for a 64-QAM signal. Under this setting, the average output power <inline-formula> <tex-math>$(mathbf {P_{avg}})$ </tex-math></inline-formula> is measured at 11.3 dBm with an RMS error vector magnitude (EVM) of −24.5 dB and an average PAE of 15.5%. The PA is fabricated in Global Foundries 45-nm-SOI technology with a compact area of 0.27 mm2. To the best of the authors’ knowledge, this work is the first to demonstrate robust performance for Doherty PAs across PVT variations.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"41-44"},"PeriodicalIF":2.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-10DOI: 10.1109/LSSC.2025.3528005
Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao
A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.
{"title":"A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique","authors":"Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao","doi":"10.1109/LSSC.2025.3528005","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528005","url":null,"abstract":"A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"45-48"},"PeriodicalIF":2.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-09DOI: 10.1109/LSSC.2025.3527533
Ali Ameri;Ali M. Niknejad
A single-stage frequency quadrupler operating in the 199–219-GHz frequency range is presented. The quadrupler utilizes a second harmonic trap and recycles the trapped power to generate additional power toward the desired fourth harmonic. The quadrupler has a peak power of −2.54 dBm while consuming 54 mW, resulting in a maximum efficiency $eta _{mathrm {MAX}}=1.03%$ . The circuit occupies an area of $370~mu $ m $times $ $240~mu $ m, the smallest footprint among the reported sub-THz frequency quadruplers. An on-chip LC oscillator and a tuned buffer provide the input signal to the quadrupler, constituting a fully integrated system.
{"title":"A Sub-THz Harmonic Recycling Single-Stage Frequency Quadrupler in CMOS 28-nm Technology","authors":"Ali Ameri;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3527533","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3527533","url":null,"abstract":"A single-stage frequency quadrupler operating in the 199–219-GHz frequency range is presented. The quadrupler utilizes a second harmonic trap and recycles the trapped power to generate additional power toward the desired fourth harmonic. The quadrupler has a peak power of −2.54 dBm while consuming 54 mW, resulting in a maximum efficiency <inline-formula> <tex-math>$eta _{mathrm {MAX}}=1.03%$ </tex-math></inline-formula>. The circuit occupies an area of <inline-formula> <tex-math>$370~mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times $ </tex-math></inline-formula> <inline-formula> <tex-math>$240~mu $ </tex-math></inline-formula>m, the smallest footprint among the reported sub-THz frequency quadruplers. An on-chip LC oscillator and a tuned buffer provide the input signal to the quadrupler, constituting a fully integrated system.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"37-40"},"PeriodicalIF":2.2,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/LSSC.2025.3527153
Shota Konno;Zachary J. Ellis;Anupam Golder;Sigang Ryu;Daniel Dinu;Avinash Varna;Sanu Mathew;Arijit Raychowdhury
This letter describes a delta-sigma ADC-based power-side-channel-attack sensor. Use of 64 sampling capacitors allows the use of over-sampling architecture even with a decoupling capacitor connected to the power supply. The LDO with low-leakage S/H is used as a driver for the integrator’s amplifier to minimize the offset error. A differential conversion method utilizing dual-integrate capacitors (CAPs) provides signal processing to compensate for drift due to supply voltage (VDD) variations. The prototype sensor chip fabricated in 65-nm CMOS has a worst-case detection accuracy of 98.7%, including VDD variations, for an insertion resistance >${=}0.25~Omega $ and a power consumption of $50~mu $ W at 1.0-V operation.
{"title":"A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor","authors":"Shota Konno;Zachary J. Ellis;Anupam Golder;Sigang Ryu;Daniel Dinu;Avinash Varna;Sanu Mathew;Arijit Raychowdhury","doi":"10.1109/LSSC.2025.3527153","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3527153","url":null,"abstract":"This letter describes a delta-sigma ADC-based power-side-channel-attack sensor. Use of 64 sampling capacitors allows the use of over-sampling architecture even with a decoupling capacitor connected to the power supply. The LDO with low-leakage S/H is used as a driver for the integrator’s amplifier to minimize the offset error. A differential conversion method utilizing dual-integrate capacitors (CAPs) provides signal processing to compensate for drift due to supply voltage (VDD) variations. The prototype sensor chip fabricated in 65-nm CMOS has a worst-case detection accuracy of 98.7%, including VDD variations, for an insertion resistance ><inline-formula> <tex-math>${=}0.25~Omega $ </tex-math></inline-formula> and a power consumption of <inline-formula> <tex-math>$50~mu $ </tex-math></inline-formula>W at 1.0-V operation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"57-60"},"PeriodicalIF":2.2,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter uses 113-Gb/s PAM4 transceiver in 5-nm CMOS to demonstrate a 1.8-Tb/s chiplet, over die-to-die extremely short-reach (XSR) intrapackage links, in an 8-port configuration. The 16-channels range from 1 to 12 dB of loss at $F_{textrm {baud}}/2$ . The chiplet performance over these channels is better than $textrm {BER}lt 10^{-9}$ , while consuming <1.1-pJ/b power and 0.22-mm2 area per lane. The performance targets are achieved using an transceiver equalization strategy which minimizes 0.5-UI ISI by design in the data path and using a LUT-based TX FFE-3 for signal equalization and envelope adaptation.
{"title":"A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS","authors":"G. Gangasani;A. Mostafa;A. Singh;D. Storaska;D. Prabakaran;K. Mohammad;M. Baecher;M. Shannon;M. Sorna;M. Wielgos;P. Jenkins;P. Ramakrishna;U. Shukla","doi":"10.1109/LSSC.2025.3526877","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3526877","url":null,"abstract":"This letter uses 113-Gb/s PAM4 transceiver in 5-nm CMOS to demonstrate a 1.8-Tb/s chiplet, over die-to-die extremely short-reach (XSR) intrapackage links, in an 8-port configuration. The 16-channels range from 1 to 12 dB of loss at <inline-formula> <tex-math>$F_{textrm {baud}}/2$ </tex-math></inline-formula>. The chiplet performance over these channels is better than <inline-formula> <tex-math>$textrm {BER}lt 10^{-9}$ </tex-math></inline-formula>, while consuming <1.1-pJ/b power and 0.22-mm2 area per lane. The performance targets are achieved using an transceiver equalization strategy which minimizes 0.5-UI ISI by design in the data path and using a LUT-based TX FFE-3 for signal equalization and envelope adaptation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"33-36"},"PeriodicalIF":2.2,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents an 8-bit 2.6-GS/s 8-way time-interleaved (TI) analog-to-digital converter (ADC) in 65-nm CMOS. The proposed dynamic current integrating sampler (DCIS) implements the functionality of input buffer and anti-aliasing filter, and eliminates the memory effect caused by parasitic capacitance. It breaks through the limitations of conventional CIS in terms of power consumption, output swing, and bandwidth. A global master sampling network with charge sharing is adopted to alleviate the impact of timing skew. The measured results show that the TI-ADC achieves an SFDR of 50.01 dB and SNDR of 41.29 dB with Nyquist input, respectively. The total power consumption is 28.88 mW, which corresponds to a Walden figure of merit of 117.2 fJ/conv.-step.
{"title":"A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler","authors":"Dengquan Li;Maowen Qian;Depan Li;Hongzhi Liang;Zhangming Zhu","doi":"10.1109/LSSC.2024.3523509","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3523509","url":null,"abstract":"This letter presents an 8-bit 2.6-GS/s 8-way time-interleaved (TI) analog-to-digital converter (ADC) in 65-nm CMOS. The proposed dynamic current integrating sampler (DCIS) implements the functionality of input buffer and anti-aliasing filter, and eliminates the memory effect caused by parasitic capacitance. It breaks through the limitations of conventional CIS in terms of power consumption, output swing, and bandwidth. A global master sampling network with charge sharing is adopted to alleviate the impact of timing skew. The measured results show that the TI-ADC achieves an SFDR of 50.01 dB and SNDR of 41.29 dB with Nyquist input, respectively. The total power consumption is 28.88 mW, which corresponds to a Walden figure of merit of 117.2 fJ/conv.-step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"29-32"},"PeriodicalIF":2.2,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-25DOI: 10.1109/LSSC.2024.3522785
Hing Tai Chen;Xun Liu;Ka Nang Leung
A capacitorless analog low-dropout regulator (CL-LDO) with cascade-inverter-based pseudo-power transistor is presented in this letter. The proposed architecture supports ultralow-voltage operation, fast transient response, high current efficiency, and high loop gain with low quiescent current along the full load range. The proposed CL-LDO can be easily implemented without any external transient-enhancement circuit. The circuit is fabricated in a 65-nm LP CMOS process with an active area of 0.00782 mm2. The minimum supply voltage can be as low as 0.5 V. The minimum dropout voltage is 20 mV. Under a 1-V supply, the undershoot voltage with 100-mV dropout voltage is 87 mV and settles down within 10 ns when the load current increases from $100~boldsymbol {mu }$ A to 50 mA within 5-ns edge time. The measured quiescent current is $4~boldsymbol {mu }$ A. The transient figure of merit is 1.48 fs.
{"title":"A 1.48-fs FoM Analog Capacitorless-LDO With Cascade-Inverter-Based Pseudo-Power Transistor","authors":"Hing Tai Chen;Xun Liu;Ka Nang Leung","doi":"10.1109/LSSC.2024.3522785","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3522785","url":null,"abstract":"A capacitorless analog low-dropout regulator (CL-LDO) with cascade-inverter-based pseudo-power transistor is presented in this letter. The proposed architecture supports ultralow-voltage operation, fast transient response, high current efficiency, and high loop gain with low quiescent current along the full load range. The proposed CL-LDO can be easily implemented without any external transient-enhancement circuit. The circuit is fabricated in a 65-nm LP CMOS process with an active area of 0.00782 mm2. The minimum supply voltage can be as low as 0.5 V. The minimum dropout voltage is 20 mV. Under a 1-V supply, the undershoot voltage with 100-mV dropout voltage is 87 mV and settles down within 10 ns when the load current increases from \u0000<inline-formula> <tex-math>$100~boldsymbol {mu }$ </tex-math></inline-formula>\u0000 A to 50 mA within 5-ns edge time. The measured quiescent current is \u0000<inline-formula> <tex-math>$4~boldsymbol {mu }$ </tex-math></inline-formula>\u0000 A. The transient figure of merit is 1.48 fs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"25-28"},"PeriodicalIF":2.2,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142937889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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