Pub Date : 2026-01-20DOI: 10.1109/LSSC.2026.3656180
Yanquan Luo;Mingtao Zhan;Yi Zhong;Nan Sun
This letter presents a power-efficient hybrid ADC architecture: a low-resolution continuous-time (CT) delta-sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback (DCD FB) provides a high jitter-immunity; the quantization of the backend is mainly performed by SAR ADCs, providing a high power efficiency. Capacitor flipping is proposed in the frontend to implement an intrinsically linear 1.5b DCD FB. Nested time-interleaving is proposed in the backend in order to assign the major quantization work to SAR ADCs. Primary–secondary sampling with improved timing is utilized to eliminate timing skew issue while gain more available sampling time and relax backend noise requirement. The ADC is fabricated in 28-nm CMOS process and achieves 70.9-dB SNDR in 300-MHz BW with 39.4-mW power consumption, yielding 169.7-dB Schreier FoM, and the band-edge performance is preserved up to 200 fs, rms clock jitter.
{"title":"A 39.4-mW 300 MHz-BW 70.9 dB-SNDR Hybrid ADC With Resistive Input and 200 fs, rms-Jitter Tolerance","authors":"Yanquan Luo;Mingtao Zhan;Yi Zhong;Nan Sun","doi":"10.1109/LSSC.2026.3656180","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3656180","url":null,"abstract":"This letter presents a power-efficient hybrid ADC architecture: a low-resolution continuous-time (CT) delta-sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback (DCD FB) provides a high jitter-immunity; the quantization of the backend is mainly performed by SAR ADCs, providing a high power efficiency. Capacitor flipping is proposed in the frontend to implement an intrinsically linear 1.5b DCD FB. Nested time-interleaving is proposed in the backend in order to assign the major quantization work to SAR ADCs. Primary–secondary sampling with improved timing is utilized to eliminate timing skew issue while gain more available sampling time and relax backend noise requirement. The ADC is fabricated in 28-nm CMOS process and achieves 70.9-dB SNDR in 300-MHz BW with 39.4-mW power consumption, yielding 169.7-dB Schreier FoM, and the band-edge performance is preserved up to 200 fs, rms clock jitter.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"61-64"},"PeriodicalIF":2.0,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-20DOI: 10.1109/LSSC.2026.3656261
Mohammadreza Zeinali;Sudhakar Pamarti
This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented to demonstrate the concept. The on-chip calibration loop iteratively measures and programs each CTT using short high-voltage pulses until the CTT current matches a reference, achieving device-level current uniformity. Measurement results show an $8times $ reduction in current-source mismatch and linearity improvements to 0.1/0.5 LSB DNL/INL. The proposed approach provides a scalable, low-cost, and nonvolatile solution for analog calibration in deeply scaled CMOS technologies.
{"title":"On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC","authors":"Mohammadreza Zeinali;Sudhakar Pamarti","doi":"10.1109/LSSC.2026.3656261","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3656261","url":null,"abstract":"This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented to demonstrate the concept. The on-chip calibration loop iteratively measures and programs each CTT using short high-voltage pulses until the CTT current matches a reference, achieving device-level current uniformity. Measurement results show an <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> reduction in current-source mismatch and linearity improvements to 0.1/0.5 LSB DNL/INL. The proposed approach provides a scalable, low-cost, and nonvolatile solution for analog calibration in deeply scaled CMOS technologies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"53-56"},"PeriodicalIF":2.0,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-14DOI: 10.1109/LSSC.2026.3654239
Hongyu Lu;Nader Fathy;Patrick P. Mercier
This letter presents a low-jitter digital harmonic-mixing fractional-$N$ phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that would otherwise dominate the in-band jitter, the sinusoidal reference is buffered by a linear source follower, in contrast to the inverters used in other LC-oscillator-based harmonic-mixing PLLs. Implemented in 65 nm CMOS, the proposed PLL achieves 603.8 fs root-mean-square jitter with a 100 MHz integration bandwidth. It occupies $0.12~text {mm}^{2}$ of silicon area and consumes 12.72 mW of power.
{"title":"A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL","authors":"Hongyu Lu;Nader Fathy;Patrick P. Mercier","doi":"10.1109/LSSC.2026.3654239","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3654239","url":null,"abstract":"This letter presents a low-jitter digital harmonic-mixing fractional-<inline-formula> <tex-math>$N$ </tex-math></inline-formula> phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that would otherwise dominate the in-band jitter, the sinusoidal reference is buffered by a linear source follower, in contrast to the inverters used in other LC-oscillator-based harmonic-mixing PLLs. Implemented in 65 nm CMOS, the proposed PLL achieves 603.8 fs root-mean-square jitter with a 100 MHz integration bandwidth. It occupies <inline-formula> <tex-math>$0.12~text {mm}^{2}$ </tex-math></inline-formula> of silicon area and consumes 12.72 mW of power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"57-60"},"PeriodicalIF":2.0,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-12DOI: 10.1109/LSSC.2026.3653014
Alin Thomas Tharakan;Cong Huang;Yiheng Fu;Horacio Londoño Ramírez;Stéphanie P. Lacour;Mahsa Shoaran
This letter presents an 8-channel current-mode stimulator achieving a ±10.2 V voltage compliance in a standard CMOS process, supporting up to 4.5 mA stimulation current per channel. The proposed dynamic charge pump (DCP), which adaptively sizes its switches based on the stimulation current, helps achieve ~15% higher power efficiency at low currents compared to conventional approaches. We further propose an ADC-based time-division multiplexed one-shot charge balancing (CB) scheme, where the duration of the second phase is adaptively adjusted to achieve near-zero residual charge on the electrode-tissue interface (ETI). The proposed CB scheme has been validated over a wide range of ETI impedances and achieves a residual voltage below 6mV with an area overhead of only 0.024 mm2/channel.
{"title":"A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue","authors":"Alin Thomas Tharakan;Cong Huang;Yiheng Fu;Horacio Londoño Ramírez;Stéphanie P. Lacour;Mahsa Shoaran","doi":"10.1109/LSSC.2026.3653014","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3653014","url":null,"abstract":"This letter presents an 8-channel current-mode stimulator achieving a ±10.2 V voltage compliance in a standard CMOS process, supporting up to 4.5 mA stimulation current per channel. The proposed dynamic charge pump (DCP), which adaptively sizes its switches based on the stimulation current, helps achieve ~15% higher power efficiency at low currents compared to conventional approaches. We further propose an ADC-based time-division multiplexed one-shot charge balancing (CB) scheme, where the duration of the second phase is adaptively adjusted to achieve near-zero residual charge on the electrode-tissue interface (ETI). The proposed CB scheme has been validated over a wide range of ETI impedances and achieves a residual voltage below 6mV with an area overhead of only 0.024 mm2/channel.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"49-52"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-12DOI: 10.1109/LSSC.2026.3651909
Lautaro N. Petrauskas;Bahman K. Boroujeni;Frank Ellinger
In this work, a cross-coupled voltage-controlled oscillator (VCO) for the high frequency RFID and citizen bands (CBs) is investigated, and implemented on a flexible Indium gallium zinc oxide thin film transistor (TFT) technology. To circumvent the challenges of integrating passive components in this frequency range and minimize the circuit’s footprint, the resonant tank is designed as a parallel connection of an active inductor with a metal oxide semiconductor capacitor - yielding a total area of $mathrm {200~mu text {m} }$ by $mathrm {330~mu text {m} }$ . The VCO can operate in the CB mode at 10 V power supply, boasting a tuning range from 26.9 MHz to 27.7 MHz and a dc power of 1.93 mW, or in the RFID mode from a 4 V supply, obtaining a 12.9 MHz - 13.6 MHz range at $mathrm {140~mu text {W} }$ dc power. To the best of the authors’ knowledge, this circuit possesses the highest figure-of-merit (frequency/total power), and overall highest oscillation frequency for VCOs reported up to date in comparable technologies.
在这项工作中，研究了一种用于高频RFID和公民波段（CBs）的交叉耦合压控振荡器（VCO），并在柔性铟镓锌氧化物薄膜晶体管（TFT）技术上实现。为了避免在此频率范围内集成无源元件的挑战并最大限度地减少电路的占地面积，谐振槽被设计为有源电感器与金属氧化物半导体电容器的并联连接-产生总面积$ mathm {200~mu text {m}}$ × $ mathm {330~mu text {m}}$。该VCO可以在10 V电源下工作于CB模式，具有26.9 MHz至27.7 MHz的调谐范围和1.93 mW的直流功率，或在4 V电源下工作于RFID模式，在$ mathm {140~mu text {W}}$直流功率下获得12.9 MHz至13.6 MHz的范围。据作者所知，该电路具有最高的性能值（频率/总功率），并且在同类技术中报道的vco的总体最高振荡频率。
{"title":"Dual-Band Voltage-Controlled Oscillator for CB and HF RFID Bands in a Flexible IGZO Technology","authors":"Lautaro N. Petrauskas;Bahman K. Boroujeni;Frank Ellinger","doi":"10.1109/LSSC.2026.3651909","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3651909","url":null,"abstract":"In this work, a cross-coupled voltage-controlled oscillator (VCO) for the high frequency RFID and citizen bands (CBs) is investigated, and implemented on a flexible Indium gallium zinc oxide thin film transistor (TFT) technology. To circumvent the challenges of integrating passive components in this frequency range and minimize the circuit’s footprint, the resonant tank is designed as a parallel connection of an active inductor with a metal oxide semiconductor capacitor - yielding a total area of <inline-formula> <tex-math>$mathrm {200~mu text {m} }$ </tex-math></inline-formula> by <inline-formula> <tex-math>$mathrm {330~mu text {m} }$ </tex-math></inline-formula>. The VCO can operate in the CB mode at 10 V power supply, boasting a tuning range from 26.9 MHz to 27.7 MHz and a dc power of 1.93 mW, or in the RFID mode from a 4 V supply, obtaining a 12.9 MHz - 13.6 MHz range at <inline-formula> <tex-math>$mathrm {140~mu text {W} }$ </tex-math></inline-formula> dc power. To the best of the authors’ knowledge, this circuit possesses the highest figure-of-merit (frequency/total power), and overall highest oscillation frequency for VCOs reported up to date in comparable technologies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"33-36"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-12DOI: 10.1109/LSSC.2026.3652323
Hsi-Hao Huang;Zong-Rui Cao;Ying-Ying Cheng;Jia-Yu Lin;Chen-Yi Lee
This letter presents a low pixel-to-pixel variation (PPV) time-to-digital converter (TDC) array designed for light detection and ranging (LiDAR) applications. The TDC array is implemented in a 0.18-$mu $ m HV CMOS process, integrated with a single-photon avalanche diode (SPAD) array. SPAD-based LiDAR systems require high-precision timing resolution across the entire sensing array, which is challenging due to process, voltage, and temperature (PVT) variations. To mitigate this issue, we propose a TDC array architecture featuring a single global timer (GT) circuit that controls the entire array. The GT comprises a differential gated ring oscillator (DGRO)-based all-digital frequency-locked loop (ADFLL) and a 16-to-5 encoder, which drives 32 time-sampling circuits through a buffer tree. The ADFLL ensures precise and uniform timing resolution over the measurement period, while the encoder and buffer tree ensure that the fine timing signal is distributed to the entire TDC array with minimal PPV. The total number of TDC output bits is 12, and the effective number of bits (ENOB) is 11.68. Measurement results indicate a PPV of 0.056%, a differential nonlinearity (DNL) of–0.99/+ 2.53 LSB, an integral nonlinearity (INL) of–2.01/+ 5.21 LSB, a resolution of 49.48 ps, and a full-scale range (FSR) of 202.65 ns.
{"title":"A 1×32 TDC Array With 0.056% Pixel-to-Pixel Variation Using a Global Timer Architecture for LiDAR Applications","authors":"Hsi-Hao Huang;Zong-Rui Cao;Ying-Ying Cheng;Jia-Yu Lin;Chen-Yi Lee","doi":"10.1109/LSSC.2026.3652323","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3652323","url":null,"abstract":"This letter presents a low pixel-to-pixel variation (PPV) time-to-digital converter (TDC) array designed for light detection and ranging (LiDAR) applications. The TDC array is implemented in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m HV CMOS process, integrated with a single-photon avalanche diode (SPAD) array. SPAD-based LiDAR systems require high-precision timing resolution across the entire sensing array, which is challenging due to process, voltage, and temperature (PVT) variations. To mitigate this issue, we propose a TDC array architecture featuring a single global timer (GT) circuit that controls the entire array. The GT comprises a differential gated ring oscillator (DGRO)-based all-digital frequency-locked loop (ADFLL) and a 16-to-5 encoder, which drives 32 time-sampling circuits through a buffer tree. The ADFLL ensures precise and uniform timing resolution over the measurement period, while the encoder and buffer tree ensure that the fine timing signal is distributed to the entire TDC array with minimal PPV. The total number of TDC output bits is 12, and the effective number of bits (ENOB) is 11.68. Measurement results indicate a PPV of 0.056%, a differential nonlinearity (DNL) of–0.99/+ 2.53 LSB, an integral nonlinearity (INL) of–2.01/+ 5.21 LSB, a resolution of 49.48 ps, and a full-scale range (FSR) of 202.65 ns.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"41-44"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter presents an approximate digital compute-in-memory (CIM) macro for low-power edge AI inference. It introduces three hierarchical innovations: 1) novel fused approximate multiply-add units (FAMUs) that reduces power and area consumption; 2) a bit-critical weight allocation architecture that optimally balances accuracy and hardware cost; and 3) a dynamic sparsity-adaptive configuration method to minimize accuracy loss in real-time. The macro achieves an energy efficiency of 60.35 TOPS/W and an area efficiency of 1105 GOPS/mm2 for INT8 MACs, outperforming prior works. It attains negligible accuracy degradation on multiple mainstream datasets and suits well for edge AI inference.
{"title":"An Approximate Digital CIM Macro With Low-Power Multiply-Add Units and Dynamic Sparse-Adaptive Configuring for Edge AI Inference","authors":"Xiaofeng Li;Yi Zhan;Purui Zhu;Rui Zhou;Jiayin Song;Heng You;Yumei Zhou;Shushan Qiao","doi":"10.1109/LSSC.2026.3652570","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3652570","url":null,"abstract":"This letter presents an approximate digital compute-in-memory (CIM) macro for low-power edge AI inference. It introduces three hierarchical innovations: 1) novel fused approximate multiply-add units (FAMUs) that reduces power and area consumption; 2) a bit-critical weight allocation architecture that optimally balances accuracy and hardware cost; and 3) a dynamic sparsity-adaptive configuration method to minimize accuracy loss in real-time. The macro achieves an energy efficiency of 60.35 TOPS/W and an area efficiency of 1105 GOPS/mm2 for INT8 MACs, outperforming prior works. It attains negligible accuracy degradation on multiple mainstream datasets and suits well for edge AI inference.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"45-48"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various static random access memory arrays, limiting their effectiveness. This restricts the power and area benefits that could be gained from an in-situ, memory circuit-assist enable/disable mechanism. To address this, we propose a novel voltage crossover-based memory assist switching circuit implemented in Intel 18A-RibbonFET technology featuring backside power delivery. Its $150times $ area efficiency enables independent placement within memory blocks, offering 19% array-level power and 17% performance improvements. Silicon measurements show tight variation control and strong simulation correlation.
{"title":"A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology","authors":"Saroj Satapathy;Amlan Ghosh;John Riley;Jalal Quadri;Jaydeep Kulkarni;Feroze Merchant","doi":"10.1109/LSSC.2026.3652110","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3652110","url":null,"abstract":"Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various static random access memory arrays, limiting their effectiveness. This restricts the power and area benefits that could be gained from an in-situ, memory circuit-assist enable/disable mechanism. To address this, we propose a novel voltage crossover-based memory assist switching circuit implemented in Intel 18A-RibbonFET technology featuring backside power delivery. Its <inline-formula> <tex-math>$150times $ </tex-math></inline-formula> area efficiency enables independent placement within memory blocks, offering 19% array-level power and 17% performance improvements. Silicon measurements show tight variation control and strong simulation correlation.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"37-40"},"PeriodicalIF":2.0,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-02DOI: 10.1109/LSSC.2025.3650657
D. Cerviño Fungueiriño;L. A. Enthoven;J. van Staveren;M. Babaie;F. Sebastiano
This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5 K. By adopting sensing elements (CMOS bulk diodes, pMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order sigma–delta readout and cryogenic-aware design techniques, the sensor achieves a maximum error of ±0.73 K (four samples and two-point trim), a resolution below 0.05 K for a 102.4-ms readout duration, and a power consumption of $mathrm {15.5~mu text {W} }$ ($mathrm {93.5~mu text {W} }$ ) at 5 K (296 K).
这项工作提出了一种低温cmos智能温度传感器，工作温度从室温降至5 K。该传感器采用了克服Si BJTs低温性能差的传感元件（CMOS体二极管、弱反转的pMOS/DTMOS）、稳健的开关电容二阶sigma-delta读出和低温感知设计技术，最大误差为±0.73 K(4个样本和两点trim)，读取时间为102.4 ms，分辨率低于0.05 K, 5 K （296 K）时功耗为$ mathm {15.5~mu text {W}}$ （$ mathm {93.5~mu text {W}}$）。
{"title":"A Cryo-CMOS Smart Temperature Sensor for the Ultrawide Temperature Range From 5 K to 296 K","authors":"D. Cerviño Fungueiriño;L. A. Enthoven;J. van Staveren;M. Babaie;F. Sebastiano","doi":"10.1109/LSSC.2025.3650657","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3650657","url":null,"abstract":"This work presents a cryo-CMOS smart temperature sensor operating from room temperature down to 5 K. By adopting sensing elements (CMOS bulk diodes, pMOS/DTMOS in weak inversion) that circumvent the poor cryogenic performance of Si BJTs, a robust switched-capacitor second-order sigma–delta readout and cryogenic-aware design techniques, the sensor achieves a maximum error of ±0.73 K (four samples and two-point trim), a resolution below 0.05 K for a 102.4-ms readout duration, and a power consumption of <inline-formula> <tex-math>$mathrm {15.5~mu text {W} }$ </tex-math></inline-formula> (<inline-formula> <tex-math>$mathrm {93.5~mu text {W} }$ </tex-math></inline-formula>) at 5 K (296 K).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"29-32"},"PeriodicalIF":2.0,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1109/LSSC.2025.3646815
Chaorong Wang;Quan Pan;Xiaohu Fang
This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard $pi $ -type equivalent circuits often suffer from bandwidth degradation due to the parasitic inductance at the isolation path. To overcome these limitations, a novel SPDT architecture based on modified $pi $ -networks is proposed. This approach incorporates the parasitic inductance of the isolation path into the $pi $ -network design, effectively enhancing the bandwidth performance without increasing circuit complexity. For validation, an SPDT switch was implemented using a 0.15-$mu $ m GaN MMIC process, covering the 10–28 GHz band. Measurement results confirm that the switch achieves an insertion loss below 2.1 dB, return loss better than 12 dB and isolation greater than 42 dB, with a compact core chip area of only 0.62 mm2.
本文介绍了针对Ku-Ka频段的宽带和紧凑型毫米波（mm波）单极双掷（SPDT）开关的设计方法。基于四分之一波长传输线的传统SPDT开关通常占用大量芯片面积，而利用标准$pi $型等效电路的替代设计通常由于隔离路径上的寄生电感而导致带宽下降。为了克服这些限制，提出了一种基于改进$pi $ -网络的SPDT架构。该方法将隔离路径的寄生电感集成到$pi $ -网络设计中，在不增加电路复杂性的情况下有效地提高了带宽性能。为了验证，使用0.15- $mu $ m GaN MMIC工艺实现了SPDT开关，覆盖10-28 GHz频段。测量结果证实，该开关的插入损耗低于2.1 dB，回波损耗优于12 dB，隔离度大于42 dB，核心芯片面积仅为0.62 mm2。
{"title":"A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks","authors":"Chaorong Wang;Quan Pan;Xiaohu Fang","doi":"10.1109/LSSC.2025.3646815","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3646815","url":null,"abstract":"This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-type equivalent circuits often suffer from bandwidth degradation due to the parasitic inductance at the isolation path. To overcome these limitations, a novel SPDT architecture based on modified <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-networks is proposed. This approach incorporates the parasitic inductance of the isolation path into the <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-network design, effectively enhancing the bandwidth performance without increasing circuit complexity. For validation, an SPDT switch was implemented using a 0.15-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaN MMIC process, covering the 10–28 GHz band. Measurement results confirm that the switch achieves an insertion loss below 2.1 dB, return loss better than 12 dB and isolation greater than 42 dB, with a compact core chip area of only 0.62 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"21-24"},"PeriodicalIF":2.0,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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