Analog Multiplexer for Performance Enhancement of Digital-to-Analog Converters and Experimental 2-to-1 Time Interleaving in 28-nm FD-SOI CMOS

Abstract

To enhance the performance of digital-to-analog converters (DACs), time interleaving by an analog multiplexer (AMUX) provides a powerful concept. Next to an increased sampling rate, potential signal quality improvement as well as a sin( ${x}$ )/ ${x}$ roll-off shift due to the nonlinear switching operation enabling a true bandwidth extension can be achieved. In this letter, an integrated AMUX in a 28-nm CMOS technology is presented. The fundamental roll-off shift is deduced from a general mathematical model. In measurements, the roll-off shift as well as improvements of the edge jitter of pulse-amplitude modulated (PAM) signals due to the AMUX are demonstrated at a sampling rate of 100GS/s. Compared to single-DAC operation at 50GS/s, the total edge jitter of a PAM-2 signal can be improved from a standard deviation of about 1.27ps to about 0.56ps at 100GS/s with AMUX operation in the given system. Finally, switching operation of the AMUX at 126GS/s is shown demonstrating the potential of the concept.