Reliable Backside IC Preparation Down to STI Level Using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry

Abstract

Abstract When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.