Finite Element Analysis (FEA) and Fractography : Complementary Methods in Understanding the Factors Resulting to Hairline Die Crack on Chip-On-Lead (COL) Devices

Abstract

Abstract Several failures in Chip-On-Lead (COL) package from the customer were returned for Failure Analysis (FA). Containment activities were able to find similar failures. The connectivity of the silicon die to the leads uses gold wire. The die is in live bug position with respect to the package and is being held in place using non-conductive die attach epoxy. The identification of the Failure Mechanism (FMECH) utilized analysis flow involving non-destructive and destructive FA techniques. A hairline crack was found on the die between the two (2) corner pins. Based on lot history reviews, hairline die crack had a very low detectability at electrical test. Further collaboration with the process owners showed the need to identify the crack initiation, propagation and the factors that could result to this FMECH. Analysis of fracture or fractography was utilized in identifying the crack initiation point and propagation. Due to low detectability, identifying the factors resulting to die crack would require several evaluations and process mappings. Finite element analysis (FEA) was utilized to create models and simulation to identify factors that would result to highly stressed area identified through fractography. These additional data for the hairline crack were vital on the identification of root cause and formulation of corrective/preventive actions.