Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons

IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-10-16 DOI:10.1109/JETCAS.2023.3325158
Hao Jiang;Jikai Lu;Chenggao Zhang;Shuangzhu Tang;Junjie An;Lingli Cheng;Jian Lu;Jinsong Wei;Keji Zhou;Xumeng Zhang;Tuo Shi;Qi Liu
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Abstract

Neuromorphic computing based on spike neural networks (SNNs) exhibits great potential in reducing energy consumption in hardware systems. Resistive random-access memory (ReRAM) is regarded as a promising candidate to construct neuromorphic hardware, attributing to their high-density, nonvolatile, and compute-in-memory capability. However, the ReRAM-based neuromorphic chips are still in their infancy, cannot support multicore or with limited neuron configurability. To alleviate these problems, we propose a hybrid multicore SNN chip based on 60K-ReRAM synapses and 480-digital neurons in the 180 nm node, achieving a synaptic density of 20K bit/mm2 per core. To improve the efficiency of inter-core communication, we adopt a network-on-chip architecture with a bit character encoding strategy. In addition, an adaptive multiplier-less digital neuron is designed to support both Izhikevich and leaky integrate-and-fire models through register bit control, meeting different application scenarios. Finally, we evaluate the performance of our chip on the MNIST dataset recognition tasks, achieving 97.65% accuracy. Also, a minimum energy per synaptic operation (SOP) of 6.6 pJ in the 180 nm node is obtained, outperforming the TrueNorth’s 26 pJ in 28 nm. These results show that our design has a great potential for large-scale SNN implementations and may pave the way for designing high-efficient neuromorphic hardware with ReRAM technology.
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采用 ReRAM 突触和数字神经元的 180 纳米多核尖峰神经形态芯片
基于尖峰神经网络(SNN)的神经形态计算在降低硬件系统能耗方面具有巨大潜力。电阻式随机存取存储器(ReRAM)因其高密度、非易失性和内存计算能力而被视为构建神经形态硬件的理想候选方案。然而,基于 ReRAM 的神经形态芯片仍处于起步阶段,不能支持多核或神经元可配置性有限。为了缓解这些问题,我们提出了一种基于 60K-ReRAM 突触和 480 个数字神经元的混合多核 SNN 芯片,该芯片采用 180 纳米节点,每个内核的突触密度达到 20K 比特/平方毫米。为了提高内核间通信的效率,我们采用了带有位字符编码策略的片上网络架构。此外,我们还设计了一种自适应无乘法器数字神经元,通过寄存器位控制,同时支持 Izhikevich 和泄漏积分发射模型,以满足不同的应用场景。最后,我们评估了芯片在 MNIST 数据集识别任务中的性能,准确率达到 97.65%。此外,在 180 纳米节点上,每次突触操作(SOP)的最小能量为 6.6 pJ,优于 TrueNorth 在 28 纳米节点上的 26 pJ。这些结果表明,我们的设计在大规模 SNN 实现方面具有巨大潜力,并可能为利用 ReRAM 技术设计高效神经形态硬件铺平道路。
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CiteScore
8.50
自引率
2.20%
发文量
86
期刊介绍: The IEEE Journal on Emerging and Selected Topics in Circuits and Systems is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, design, tools, and implementation of circuits and systems, spanning their theoretical foundations, applications, and architectures for signal and information processing.
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