A hardware digital fuzzy inference engine using standard integrated circuits

Sujal M. Shah, Ralph Horvath
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Abstract

The paper describes a general-purpose board-level fuzzy inference engine intended primarily for experimental and educational applications. The components are all standard TTL integrated circuits (7400 series) and CMOS RAMs (CY7C series). The engine processes 16 rules in parallel with two antecedents and one consequent per rule. The design may easily be scaled to accommodate more or fewer rules. Static RAMs are used to store membership functions of both antecedent and consequent variables. “Min-max” composition is used for inferencing, and for defuzzification, the mean of maxima strategy is used. Simulation on VALID CAE software predicts that the engine is capable of performing up to 1.56 million fuzzy logic inferences per second.

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采用标准集成电路的硬件数字模糊推理引擎
本文描述了一个通用的板级模糊推理引擎,主要用于实验和教育应用。元件均为标准TTL集成电路(7400系列)和CMOS ram (CY7C系列)。该引擎并行处理16条规则,每个规则有两个先行项和一个后项。设计可以很容易地缩放以适应更多或更少的规则。静态ram用于存储前因变量和后因变量的隶属函数。“最小-最大”组合用于推理,对于去模糊化,使用最大均值策略。在VALID CAE软件上的仿真预测,该引擎能够每秒执行多达156万次模糊逻辑推理。
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