CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit

IF 1.2 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC Iet Circuits Devices & Systems Pub Date : 2021-05-25 DOI:10.1049/cds2.12082
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引用次数: 0

Abstract

In [1], the following corrections should be noted.

This work is sponsored by the Young Faculty Research Fellowship (YFRF) of Visvesvaraya Ph.D. scheme through the grant number MLA/MUM/GA/10(37)B.

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在b[1]中,应注意以下更正。本研究由Visvesvaraya博士项目青年教师研究奖学金(YFRF)资助,资助号MLA/MUM/GA/10(37)B。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Iet Circuits Devices & Systems
Iet Circuits Devices & Systems 工程技术-工程:电子与电气
CiteScore
3.80
自引率
7.70%
发文量
32
审稿时长
3 months
期刊介绍: IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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