Optimal Design of Two-Bit QCA Comparator Circuits

Abstract

The quantum-dot cellular automata (QCA) technology is one of the technologies for CMOS replacement which work based on columbic interacts. In this study, two two-bit comparator circuits are presented based on QCA and evaluated in terms of cell count, latency, and occupied area. Moreover, this study aims to reduce the occupied area, complexity, and energy dissipation of the comparator circuits, so the two comparator circuits have different power consumption levels. The proposed two-bit comparators are more compact and perform more consistently compared to previous designs. Design parameters of the two proposed circuits are optimized by reducing the cell count and occupied area compared to previous studies. The simulation results show that the proposed designs have a completely correct performance. In the first proposed two-bit comparator, 122 cells are used on an area of 0.14 µm² with a latency of 2.25 clock cycles. The second proposed two-bit comparator uses 107 cells on an area of 0.17 µm² with a latency of 1.75 clock cycles. Moreover, the values of energy dissipation of the proposed two-bit comparators at tunneling energies of 0.5, 1, and 1.5 E_k are calculated. In the first proposed two-bit comparator, the average energy dissipation for tunneling energies of 0.5, 1, and 1.5 E_k are calculated as 161.43, 222.83 and 296.52 meV, respectively. In the second proposed two-bit comparator, the average energy dissipation for tunneling energies of 0.5, 1, and 1.5 E_k are calculated as 139.36, 192.92, and 257.06 meV, respectively.