A novel low hardware configurable ring oscillator (CRO) PUF for lightweight security applications

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Microprocessors and Microsystems Pub Date : 2023-12-23 DOI:10.1016/j.micpro.2023.104989
Husam Kareem, Dmitriy Dunaev
{"title":"A novel low hardware configurable ring oscillator (CRO) PUF for lightweight security applications","authors":"Husam Kareem,&nbsp;Dmitriy Dunaev","doi":"10.1016/j.micpro.2023.104989","DOIUrl":null,"url":null,"abstract":"<div><p>Physical unclonable function (PUF) is a promising hardware security primitive that can generate a unique secret key peculiar to each chip by extracting the differences of non-reproducible manufacturing variations for the same implementations. Although there are several types of PUF designs and structures, ring oscillator (RO) PUF is one of the most prominent PUFs due to its straightforward implementation and remarkable performance. However, the traditional RO-PUF does not support large sizes of input/output combinations or challenge-response pairs (CRPs), as it is called in the scope of PUFs. Consequently, RO-PUF is more vulnerable to adversary attacks which can reveal the PUFs’ CRPs using a machine learning approach. Increasing the size of RO-PUF's CRPs requires a high increase in the circuit size leading to unacceptable area overhead for lightweight applications. The primary technique used to increase RO-PUF CRPs’ size without increasing the size of the required hardware is to develop a configurable ring oscillator (CRO) PUF. In this paper, we propose a configurable logic unit (CLU) that can be utilized to build a low-hardware CRO-PUF. The proposed CLU consists of a 1-XOR gate and a 1-XNOR gate. Building a CRO-PUF using the proposed CLU dramatically increases the CRPs size while minimizing the required hardware. The proposed CRO-PUF achieves excellent evaluation results, with measured uniqueness of 50.1 %, uniformity of 49.45 %, and reliability of 98.33 %. These values are in close proximity to the ideal targets of 50 % for uniqueness and uniformity, and 100 % for reliability</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2023-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S014193312300234X/pdfft?md5=701fd3d90bd65a2ed764a13232d9a6bb&pid=1-s2.0-S014193312300234X-main.pdf","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessors and Microsystems","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S014193312300234X","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

Physical unclonable function (PUF) is a promising hardware security primitive that can generate a unique secret key peculiar to each chip by extracting the differences of non-reproducible manufacturing variations for the same implementations. Although there are several types of PUF designs and structures, ring oscillator (RO) PUF is one of the most prominent PUFs due to its straightforward implementation and remarkable performance. However, the traditional RO-PUF does not support large sizes of input/output combinations or challenge-response pairs (CRPs), as it is called in the scope of PUFs. Consequently, RO-PUF is more vulnerable to adversary attacks which can reveal the PUFs’ CRPs using a machine learning approach. Increasing the size of RO-PUF's CRPs requires a high increase in the circuit size leading to unacceptable area overhead for lightweight applications. The primary technique used to increase RO-PUF CRPs’ size without increasing the size of the required hardware is to develop a configurable ring oscillator (CRO) PUF. In this paper, we propose a configurable logic unit (CLU) that can be utilized to build a low-hardware CRO-PUF. The proposed CLU consists of a 1-XOR gate and a 1-XNOR gate. Building a CRO-PUF using the proposed CLU dramatically increases the CRPs size while minimizing the required hardware. The proposed CRO-PUF achieves excellent evaluation results, with measured uniqueness of 50.1 %, uniformity of 49.45 %, and reliability of 98.33 %. These values are in close proximity to the ideal targets of 50 % for uniqueness and uniformity, and 100 % for reliability

查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于轻量级安全应用的新型低硬件可配置环形振荡器 (CRO) PUF
物理不可克隆函数(PUF)是一种前景广阔的硬件安全基元,它可以通过提取相同实现方式下不可再现的制造差异,生成每个芯片特有的唯一密钥。尽管 PUF 的设计和结构有多种类型,但环形振荡器(RO)PUF 以其简单的实现方式和出色的性能成为最突出的 PUF 之一。然而,传统的环形振荡器 PUF 不支持大容量的输入/输出组合或挑战-响应对(CRP),这在 PUF 的范围内被称为 "挑战-响应对"。因此,RO-PUF 更容易受到对手攻击的影响,这些攻击可以利用机器学习方法揭示 PUF 的 CRP。要增加 RO-PUF 的 CRP,就必须大幅增加电路尺寸,从而导致轻量级应用无法接受的面积开销。在不增加所需硬件体积的情况下增加 RO-PUF CRPs 体积的主要技术是开发可配置环形振荡器 (CRO) PUF。在本文中,我们提出了一种可配置逻辑单元(CLU),可用于构建低硬件成本的 CRO-PUF。拟议的 CLU 由一个 1-XOR 门和一个 1-XNOR 门组成。使用拟议的可编程逻辑单元构建 CRO-PUF 可显著增加 CRPs 的大小,同时最大限度地减少所需的硬件。拟议的 CRO-PUF 取得了出色的评估结果,测得唯一性为 50.1%,均匀性为 49.45%,可靠性为 98.33%。这些值都非常接近理想目标,即唯一性和统一性达到 50%,可靠性达到 100%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
期刊最新文献
Algorithms for scheduling CNNs on multicore MCUs at the neuron and layer levels Low-cost constant time signed digit selection for most significant bit first multiplication Retraction notice to “A Hybrid Semantic Similarity Measurement for Geospatial Entities” [Microprocessors and Microsystems 80 (2021) 103526] A hardware architecture for single and multiple ellipse detection using genetic algorithms and high-level synthesis tools SIMIL: SIMple Issue Logic for GPUs
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1