Arrangement rule of stability regions and single-electron transfer in common-gate quadruple-dot devices for the real ratio of gate capacitances

IF 2.2 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Journal of Computational Electronics Pub Date : 2024-01-04 DOI:10.1007/s10825-023-02119-4
Shigeru Imai, Yusuke Watanabe
{"title":"Arrangement rule of stability regions and single-electron transfer in common-gate quadruple-dot devices for the real ratio of gate capacitances","authors":"Shigeru Imai, Yusuke Watanabe","doi":"10.1007/s10825-023-02119-4","DOIUrl":null,"url":null,"abstract":"<p>For single-electron transfer in common-gate multidot devices, the arrangement of stability regions along the gate voltage (<i>V</i><sub>g</sub>) axis is important because single-electron transfer occurs around the overlap of stability regions. The stability regions along the <i>V</i><sub>g</sub> axis are well known to have periodicity when the device has an integer ratio of gate capacitances (<i>C</i><sub>g</sub>). However, the arrangement rule for the real <i>C</i><sub>g</sub> ratio is unclear. In this paper, stability regions for quadruple-dot devices with symmetric <i>C</i><sub>g</sub> are exhaustively examined. The arrangement of stability regions along the <i>V</i><sub>g</sub> axis is drawn as a map of the real <i>C</i><sub>g</sub> ratio in a newly proposed diagram. Here, the arrangement for a particular <i>C</i><sub>g</sub> ratio is drawn along a straight line that passes through the origin and has a slope depending on the <i>C</i><sub>g</sub> ratio. In the diagram, stability regions are arranged two-dimensionally, and the abovementioned periodicity for integer <i>C</i><sub>g</sub> ratios clearly appears. How neighboring stability regions interrelate with each other in the diagram is mathematically examined and described in detail. Next, the sequences of tunneling events around the overlap of stability regions are investigated, and eight kinds of tunneling sequences for single-electron transfer are determined.</p>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Computational Electronics","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1007/s10825-023-02119-4","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

For single-electron transfer in common-gate multidot devices, the arrangement of stability regions along the gate voltage (Vg) axis is important because single-electron transfer occurs around the overlap of stability regions. The stability regions along the Vg axis are well known to have periodicity when the device has an integer ratio of gate capacitances (Cg). However, the arrangement rule for the real Cg ratio is unclear. In this paper, stability regions for quadruple-dot devices with symmetric Cg are exhaustively examined. The arrangement of stability regions along the Vg axis is drawn as a map of the real Cg ratio in a newly proposed diagram. Here, the arrangement for a particular Cg ratio is drawn along a straight line that passes through the origin and has a slope depending on the Cg ratio. In the diagram, stability regions are arranged two-dimensionally, and the abovementioned periodicity for integer Cg ratios clearly appears. How neighboring stability regions interrelate with each other in the diagram is mathematically examined and described in detail. Next, the sequences of tunneling events around the overlap of stability regions are investigated, and eight kinds of tunneling sequences for single-electron transfer are determined.

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共栅极四重点器件中栅极电容实数比稳定区和单电子转移的排列规则
对于共栅极多点器件中的单电子转移而言,沿栅极电压(Vg)轴的稳定区域排列非常重要,因为单电子转移发生在稳定区域重叠的周围。众所周知,当器件的栅极电容(Cg)为整数比时,沿 Vg 轴的稳定区域具有周期性。然而,实际 Cg 比的排列规则尚不清楚。本文详尽研究了具有对称 Cg 的四重点器件的稳定区域。在新提出的图表中,稳定区域沿 Vg 轴的排列被绘制成实际 Cg 比的地图。在这里,特定 Cg 比的排列是沿着通过原点的直线绘制的,其斜率取决于 Cg 比。在图中,稳定区域呈二维排列,上述整数 Cg 比的周期性清晰可见。图中相邻稳定区之间的相互关系将通过数学方法进行研究和详细描述。接着,研究了稳定区重叠周围的隧道事件序列,并确定了单电子转移的八种隧道序列。
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来源期刊
Journal of Computational Electronics
Journal of Computational Electronics ENGINEERING, ELECTRICAL & ELECTRONIC-PHYSICS, APPLIED
CiteScore
4.50
自引率
4.80%
发文量
142
审稿时长
>12 weeks
期刊介绍: he Journal of Computational Electronics brings together research on all aspects of modeling and simulation of modern electronics. This includes optical, electronic, mechanical, and quantum mechanical aspects, as well as research on the underlying mathematical algorithms and computational details. The related areas of energy conversion/storage and of molecular and biological systems, in which the thrust is on the charge transport, electronic, mechanical, and optical properties, are also covered. In particular, we encourage manuscripts dealing with device simulation; with optical and optoelectronic systems and photonics; with energy storage (e.g. batteries, fuel cells) and harvesting (e.g. photovoltaic), with simulation of circuits, VLSI layout, logic and architecture (based on, for example, CMOS devices, quantum-cellular automata, QBITs, or single-electron transistors); with electromagnetic simulations (such as microwave electronics and components); or with molecular and biological systems. However, in all these cases, the submitted manuscripts should explicitly address the electronic properties of the relevant systems, materials, or devices and/or present novel contributions to the physical models, computational strategies, or numerical algorithms.
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