Low power adders using asynchronous pipelined modified low voltage MCML for signal processing and communication applications

Abstract

Low power design features have dramatically changed since semiconductors made their move towards deep submicron technologies. In the datapath cells, power dissipation is a major concern since they make up the primitives of higher- level system architectures like microprocessors, Random Access Memory (RAM) cells and mobile architectures. By combining low voltage MOS Current Mode Logic (MCML) with two phase bundled data protocol, the manuscript describes a practical method for designing combinational circuits. Asynchronous pipeline circuits can accomplish higher throughput, reduced latency, and consume less power than synchronous pipeline circuits without experiencing clock skew problems. Muller C-elements are used to produce control signals in the handshaking path and D latches areemployed to ensure that the control signal generation proceeds in two phases. The proposed concept is implemented in 1-bit full adder and 4bit Carry Look Ahead (CLA) adder and simulated inT-SPICE using TSMC 45 nm technology library. In comparison to conventional MCML-based 4-bit CLA adder, asynchronous pipelined low voltage MCML implementation achieves 24% reduced power consumption, 19% less computation time, and 39% less Power Delay Product (PDP).