Analog Integrated Circuits and Signal Processing最新文献

Content Addressable Memory (CAM) is utilized in Artificial Neural Networks, data compression, IP packet filtering, and network routers due to its high performance in the microprocessor. However, the use of CAM is limited because of its increased power consumption, especially in high capacitive Match-Lines (ML). The activation of every comparison circuit on every clock cycle is primarily responsible for the significant power dissipation, which leads to increased recharge activity and multiple transition occurrences in the ML. In order to overcome this issue, a novel Common Match Line Scheme (CMS) with a Pull Up/Pull Down (PUPD) Circuit is proposed. The new design of the CMS CAM architecture leverages by utilizing these technique, the mismatched tagline entries are kept in the pre-discharged phases, and only the matching tagline entry gets charged. Consequently, these approaches effectively reduce pre-charge activity and mitigate evaluate-power, thereby alleviating power dissipation concerns associated with CAM 13–45% and reducing delay 3–16% while comparing to the existing architectures without significant impact on the performance of the processor. Proposed CMS CAM outperforms the existing architectures in terms of noise also with minimal area overhead and it is a technology independent one which can be used in high performance microprocessor systems.

This paper presents a sub-1-V CMOS bandgap reference circuit with ultra-low power consumption, utilizing only 9 MOS transistors. The proposed circuit achieves nano-watt power consumption by biasing all transistors in the sub-threshold region. A three-branched configuration is utilized to create the bandgap voltage reference in the circuit. The proposed architecture generates CTAT and PTAT voltages without using any op-amp and BJT. In this circuit, the cascode structure are used to improve the line sensitivity (LS). In the proposed bandgap circuit, self-biased configuration is used without using an external bias circuitry. The first branch generates PTAT current and the second and third branches generate PTAT and CTAT voltages. The bandgap circuit is designed and simulated using Cadence in TSMC 0.18 μm CMOS technology. The results of post-layout simulation indicate that the bandgap voltage reference circuit generates a voltage reference of 644 mV, with a temperature coefficient (TC) of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The proposed circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. Furthermore, the circuit exhibits a line sensitivity of 0.31%/V for power supply voltages ranging from 0.9 to 1.8 V. The Power Supply Ripple Rejection (PSRR) of the proposed circuit is about − 40 dB within the frequency range of 1–100 Hz.

This research paper demonstrates behavior of memristor emulator circuit at various input frequencies. It is a critical circuit having a vast potential for constructing digital and analog circuits, FM-to-AM converters, filters, cellular neural networks, sensors, analog circuits, and chaotic oscillators are all designed with memristor circuits. It has some unique properties such as nonlinear behaviour, analog signal processing, adaptive and reconfigurable system, memory and state retention and also high density and low power consumption. These properties build the communication system more reliable secure and more efficient. To enhance the design of the memristor model, implementation doing using analog multiplier and operational transconductance amplifier with a constant transcoductance gain is employed. In addition to the input supply voltage frequency (f) and amplitude (Vm), the operational transconductance amplifier provides a control parameter known as the transconductance (gm). Modifications in amplitude have an impact on memory resistance, and variations in biassing voltage influence transconductance (gm) of OTA. The research shows memristor-based chaotic circuit use for secure transmission system. The operational frequency that exhibits the maximum value is 10 kilohertz, accompanied by a power dissipation of 24.1 microwatts with noise (51.9text{ nV}/{text{Hz}}^{1/2}) at room temperature. This study employs a circuit electronic design automation (EDA) tool to demonstrate the behavior of a memristor circuit under varying input conditions.

This study proposes a flexible MIMO antenna with improved isolation and connected ground designed on a flexible substrate that makes it compatible with various shapes and surfaces, including curved, irregular, or non-planar structures. The suggested single unit consists of a slotted rectangular radiator on the front layer with a partial ground connected to a circular stub on the other side. As well it is created on a flexible substrate (Rogers RO3003) that has a dielectric constant (ε_r) of 3 and a thickness of 1.52 mm. The Four copies of the single unit with orthogonal orientation are added to improve the system performance. The antenna units are connected through their ground to introduce the connected ground antenna. The size of the proposed design is compact (50 × 50 × 1.524 mm³⁾. The simulating and testing results demonstrate that the antenna operates within a frequency range of 3–12 GHz and achieves a high isolation of ≥ 17 dB over most frequency range. The MIMO parameters and the radiation patterns are analyzed to evaluate the performance of the MIMO antenna. Finally, the four elements of the flexible antenna are fabricated and tested under flat and bending conditions. The simulation and testing results demonstrate that the suggested design exhibits excellent performance, such as broad bandwidth, high isolation, simple structure, and decreased correlation coefficient, which suggest it for the UWB applications and its flexibility allows it for integration into a wide range of devices, such as wearable technology, Internet of Things (IoT) devices, and curved surfaces of vehicles or aircraft.

This paper derives theoretical results for adaptive bias in Doherty amplifiers and presents the design and measurements of an integrated adaptive bias circuit tailored for high peak-to-average high bandwidth signals. Fundamental equations for output power, impedance, and efficiency of the complete Doherty amplifier are derived. Even with ideal transistor models, the Doherty amplifier is fundamentally nonlinear due to saturation of the main amplifier and class-C nonlinearity of the auxiliary. Increasing the transconductance of the auxiliary amplifier mitigates the distortion. Adaptive bias offers the possibility to control the output current characteristic of the auxiliary amplifier. This means that adaptive bias linearises and mitigates the need for an oversized auxiliary amplifier. Both methods, transconductance scaling and adaptive bias, are analysed and compared as well as having a band limited adaptive bias signal. The design of a multiple GHz bandwidth adaptive bias circuit is presented. To verify the circuit design and the theoretical predictions, an mmW Doherty amplifier in 22 nm CMOS-FD-SOI, utilizing the presented adaptive bias circuit, is measured and compared with and without adaptive bias. Comparison is conducted both using continuous-wave and modulated high bandwidth signals. Measured results confirm the predicted improvements by the adaptive bias as derived by the theoretical analysis.

This article presents the design of an integrated, frequency-programmable stimulation circuit dedicated to small rodents for the study of pulmonary arterial hypertension. A complete architecture of the stimulation circuit is proposed, based on in vivo tests that have led to the stimulation waveform specification. The circuit is designed using XFAB 0.18 µm technology. The adopted design methodology allows to reduce the power consumption of command blocks to the minimum. Post-layout simulation results shows that the pacing rate can be tuned from 450 to 600 beats per minute (bpm). The total power consumption of the stimulation circuit is 196.1 µW, with 186 µW directly consumed by the voltage multipliers, H-Bridge and pacemaker load, 10.1 µW by the kilohertz-range VCO driver, and only 8.4 nW by the ultra-low power command generator.

This paper presents a new biquad filter based on carbon nanotube field-effect transistor (CNFET) technology. Implementing various filter modes (high-pass, low-pass, band-pass, and band-stop) in four operating modes (voltage, current, transconductance, and transresistance) with a unified circuit structure is the fundamental feature of the proposed filter. The proposed universal filter is intended for commercial radio communications in the FM band to reduce power consumption and chip area occupation. The proposed circuit can adjust a wide frequency range and thus cover multiple radio channels with minimum noise and distortion on the signal. The proposed filter in 20 nm technology has been simulated using advanced design system (ADS) software to investigate the effects of high-frequency effects. The minimum power consumption is 360 nW, with a supply voltage of 0.9 V, with the ability to independently adjust the center frequency (22 MHz < f₀ < 120 MHz) and filter quality factor (0.6 < Q < 23) and the use of grounded capacitors to absorb parasitic effects are among the advantages of the proposed circuit. The proposed Gm-C circuit has the highest figure of merit (FOM) value of 318.5. Moreover, its resistance to process variations, power supply, and temperature changes demonstrates the appropriate performance of the proposed filter.

This paper presents a unique full-wave rectifier designed with the help of second generation current conveyor (CCII) which is a promising building block to design the analog circuits. The proposed circuit is designed & simulated on OrCAD/PSpice using key ICAD844 as CCII, manufactured by Analog Devices corporation. The simulated results are extracted using EDA tool for the input of different frequencies till 1 MHz. The excellent output waveforms verify the proposed circuit with the characteristics of full-wave rectifier. The hardware prototype is implemented & tested on printed circuit board using laboratory setup to validate the proposed concept. The resultant output signal is undistorted, fully rectified and maintained with sinusoidal shape for the input signal having frequency of 1.022 MHz. The metal oxide semiconductor structure with the small signal analysis of proposed circuit is also discussed.