Analog Integrated Circuits and Signal Processing最新文献

This paper presents a T-type contact coplanar waveguide (CPW) radio frequency (RF) sensor designed for the detection of liquids with high dielectric constants, ranging from 63 to 104. The resonant frequency of the CPW structure is highly sensitive to both its geometric configuration and the dielectric properties of the surrounding medium, making it particularly suitable for liquid sensing applications. Using high-frequency electromagnetic simulations, the sensor was first optimized for a specific water sample and subsequently adapted for a broader range of high-dielectric liquids. The resulting resonance frequency shift among different liquid samples ranged from a minimum of 10 MHz to a maximum of 280 MHz, demonstrating significant sensitivity. To validate the simulation results, the sensor was fabricated using a direct deposition technique, employing silver nanoparticles (AgNPs)-based ink printed onto a transparent polyethylene terephthalate substrate. This fabrication approach enables low-cost, scalable, and environmentally friendly production. Surface characterization confirmed uniform and smooth deposition of the conductive AgNP layer with ~ 450 nm thickness. Experimental testing further verified that the resonance frequency shifted predictably in response to each tested liquid, aligning closely with the simulated outcomes. This work demonstrates that the proposed T-type CPW RF sensor is a promising for liquid detection, offering potential applications in areas such as quality control, process monitoring, and biomedical diagnostics. The integration of simulation-driven design and additive manufacturing indicates the feasibility of deploying such sensors in real-world scenarios.

Several studies have shown the benefits of Machine Learning (ML) approaches for automating and improving Integrated Circuit (IC) layout processes both digital and analog. However, the challenge of data scarcity persists in electronic design, particularly when aiming to train highly accurate ML models. This paper proposes a method for enhancing VLSI circuit performance prediction through Qualitative Data Augmentation using Mixed-Decomposed Convolutional Network (VLSI-QDA-MDCN). Here, the data is collected from EDA technologies like, HSpice, Micro-Cap and Cadence Virtuoso including fourteen delay datasets derived from basic digital circuits and six frequently used analog electronic devices. The process and design factors that differentiate the training data for a given circuit topology create. However, privacy concerns and other constraints limit this data collection technique. To address these limitations, the Qualitative Data Augmentation (QDA) is performed using Mixed-Decomposed Convolutional Network (MDCN), which contributes to the enhancement of the precision of machine learning models trained on a limited dataset. The training data is obtained by simulations using 22 nm and 180 nm CMOS technology nodes from TSMC in Cadence Virtuoso, HSPICE, Microcap design environments. The proposed VLSI-QDA-MDCN method is implemented in Python. The proposed method achieves 23.62%, 25.96%, 26.23% low MSE; 34.83%, 33.02% and 25.98% low RMSE when compared with existing techniques, like QDA-VLSI-GAN, GNN-VLSI-DAT and ADED-VLSI-MMD.

This work proposes a Phase Frequency Detector (PFD) based on Dynamic Pass Transistor Logic (DPTL). Since the circuit is designed without a reset-path, the dead zone and blind zone are effectively eliminated. Due to the elimination of dead and blind zones, the (phi)-V characteristics of the PFD exhibit enhanced linearity over the range from –(pi) to (pi). To optimize the PFD, Taguchi and ANOVA statistical approaches were applied. The optimized PFD operates at a maximum-frequency of 9.1 GHz with a delay of 53.86 ps, while consuming 5.17 (mu)W of power and exhibiting a phase-noise of –156.099 dBc/Hz. Based on the proposed PFD, a GHz-range synthesizer was implemented, exhibiting a power dissipation of 7.85 mW at 1.8 V, a lock-time of 0.23 (mu)s, and a frequency tuning range of 0.5–10.44 GHz, while having an area of 0.017 mm(^{2}). The robustness of the PFD and frequency synthesizer circuits was evaluated under process, voltage, and temperature (PVT) variations for both pre- and post-layout simulations. With its wide tuning range, the proposed frequency synthesizer is well-suited for wireless communication, satellite links, radar systems, and GPS navigation.

This work introduces a novel quadruple-channel FinFET design to address the limitations of conventional MOSFETs, particularly short-channel effects. Significant performance enhancements have been achieved through rigorous optimization of key parameters such as fin width, threshold voltage ((V_{th})), Drain-Induced Barrier Lowering (DIBL), and drain current ((I_D)). For 5nm fin width, the optimized structure exhibits a low (V_{th}) of 0.31V, a minimal DIBL of 22mV/V, and a high normalized drain current of 820(mu)A/(mu)m. The 5nm structure also shown excellent transconductance of 2720(mu)S/(mu)m. The parameters obtained for 5nm show significantly improved performance as compared to Bulk-MOSFET. Furthermore, for 20nm fin width, the optimized design demonstrates a (V_{th}) of 0.247V and a drain current of 148(mu)A at a gate voltage of 0.7V. Importantly, the quadruple-channel FinFET exhibits a significantly improved (hbox {I}_{ON})/(hbox {I}_{OFF}) ratio ((29.6 times 10^5) for 5 nm fin width) and a reduced subthreshold swing (109mV/decade for 5nm fin width). These results indicate enhanced scalability and reduced leakage currents, even at smaller device dimensions, demonstrating a clear performance advantage over conventional FinFET structures. By investigating the circuit performance, the designed FET exhibits a sharp transition in its inverting behavior, a desirable characteristic for digital circuit applications. A peak gain was observed at a 5nm fin width. Transient analysis demonstrates the designed structure’s low rise and fall times, confirming its suitability for high-speed and precision applications. Specifically, for the 20nm Fin-width, a minimum rise time of 15ps and a fall time of 10ps were observed.

The increasing complexity and integration density of modern mixed-signal and high-frequency systems demand reconfigurable, precise, and fault-tolerant signal-routing architectures. Conventional switching matrices based on multiplexers or crossbar networks suffer from crosstalk, leakage, limited scalability, and weak fault tolerance, making them unsuitable for emerging precision analog platforms. Addressing these limitations, this work introduces the Diode-Based Programmable Network Array (DiProNA), a novel hybrid switching architecture that differs fundamentally from existing structures by combining MOSFET-based programmability with unidirectional diode-assisted conduction paths to achieve intrinsic fault isolation, current sharing, and enhanced thermal robustness. A comprehensive analytical model—developed using Thevenin equivalents, nodal analysis, and explicit inclusion of diode and MOSFET parasitics—is presented and validated through extensive circuit-level simulations. Clear modeling assumptions (such as quasi-static device behavior and linearized small-signal parasitics) are stated to ensure transparency and reproducibility. Quantitative comparisons with traditional multiplexer and crossbar matrices demonstrate that DiProNA achieves higher voltage accuracy, lower effective resistance, and significantly reduced short-circuit current. Series ballast resistors effectively constrain fault currents and mitigate thermal stress, enabling reliable operation under open-circuit, short-circuit, and partial-failure scenarios. Multi-source configurations further enhance efficiency and distribute power-thermal load, while dynamic evaluations confirm microsecond-level response times with minimal overshoot, supporting high-speed instrumentation front-ends. Collectively, the results position DiProNA as a scalable, efficient, and fault-tolerant routing solution suitable for adaptive data converters, SoC subsystems, wireless front-ends, and biomedical instrumentation. This work establishes DiProNA as a robust and versatile platform advancing next-generation programmable mixed-signal systems.

In mammalian hearts, the Sinoatrial (SA) node cells act as the fundamental pacemaker location. The intricate patterns of SA node activity can be elucidated by a series of differential equations featuring non-linear functions. This study presents a novel approach to improve the digital representation of the SA node cell model. The results consist of reduced hardware requirements, enhanced speed and accuracy, and lowered implementation costs. The proposed method involves converting the non-linear functions found in the original model into exponential functions represented as (2^x). This conversion gives rise to a set of mathematical equations that eliminate the need for multipliers. These equations are subsequently refined by minimizing the number of (2^x) terms, leading to a more effective emulation of the SA model’s biological characteristics. To validate the concept, the suggested model is successfully synthesized and implemented on an FPGA. The implementation outcomes demonstrate a substantial enhancement in operating frequency, showing a 3.4-fold increase compared to the original model. Moreover, there is a noticeable 47% reduction in power consumption. The reduced hardware requirements also enable running a significantly larger number of neurons, precisely 12 times more, on a single FPGA board compared to the original model.

Effective partitioning and floor planning are key issues in VLSI circuit design that directly influence performance, power consumption, and area use. The conventional methodologies tend to compromise on these factors poorly, particularly in large-scale and complicated circuit structures. To overcome this problem, a novel framework known as Dilated Causal Convolution Guided with Multi-head Decision Self-Transformer Network (D2C-GMH-DSTN) is presented. This architecture combines Dilated Causal Convolution with multi-head self-attention and is augmented by a Critic-Guided Decision Transformer. To optimize its decision-making further, the Meerkat Optimization Algorithm (MOA) is utilized. Experimental verification on typical MCNC benchmark circuits verifies the excellence of the presented approach. On the circuits S1196, S1238, S3350, and S8378, the method attains an average speed of 98.75 ms, a minimum average wire length of 28.75 m, and less power consumption as low as 1.175 W, surpassing state-of-the-art baseline methods on all dimensions. The technique offers a scalable and resilient solution with high precision, significantly enhancing design optimization results.

Research efforts have extensively shown the significant roles of unpredictable phenomena originated in nature, such as chaos, as an inspiring discipline to generate random numbers. In the current study, focusing on encryption purposes, the main strategy is to provide a keystream using Pseudo Random Number Generators (PRNGs) derived from synchronized chaotic systems. Numerous Investigations performed on the synchronized configuration of Chua’s circuit have proven the advantage of its application as a prominent chaotic system. However, the less than ideal alignment between the core objective of the research, that is offering a secure communication optionally necessitating an arbitrary distance of the correspondents, and the standard version of synchronized Chua’s circuits not fulfilling this condition pragmatically, made the authors tackle the problem analytically by using the governing equations of the circuits and creating the so-called quasi-synchronized condition between the receiving and the transmitting sides. At last, eight different mathematical schemes are designed to manipulate the numerical data provided by the Chua’s equations to generate binary sequences for encryption purposes and then the main attempt has been dedicated to the evaluation of the results and finding the optimal PRNGs by conventional standards in cryptography provided by National Institute of Standards and Technology. Finally, three of the designed schemes are chosen as the successful methods, passing randomness criteria.

This paper presents the Congestion-aware SDN–Fog with Deep Reinforcement Learning (CSFD) framework, a novel hybrid architecture that integrates SDN’s centralized control with Fog-layer adaptive learning to mitigate congestion in vehicular networks. Unlike existing DRL-based routing or SDN-only models, CSFD introduces a DRL-enabled Fog decision layer that performs congestion prediction and dynamic route optimization in coordination with SDN controllers. Simulation results demonstrate that CSFD achieves higher delivery ratio, lower latency, and reduced routing overhead compared to recent DRL and SDN–Fog baselines. This paper presents the approach, with congestion reduction SDN and Fog integration using Deep reinforcement learning to minimize the congestion in vehicular newtwork. It elucidates the intricacies of the network model, SDN processing, device management, and routing mechanisms within an SDN-enabled VANET environment, highlighting dynamic resource allocation and adaptive routing strategies. Additionally, it empowers autonomous decision-making for data scheduling and resource optimization and implements parked vehicle routing to manage communication in remote areas. The proposed approach, Speed and Position-aware Dynamic Routing (SPDR) is introduced to facilitate the efficient dissemination of Emergency Messages (EMs) on motorways. SPDR incorporates a dynamic greedy routing mechanism based on speed metrics, positional awareness, and a collaborative forwarding strategy. EMs are relayed incrementally from the source vehicle to the intended recipient through the hop-by-hop transmission. This strategy effectively mitigates the risk of selected forwarders moving out of the reception range during message forwarding, ensuring reliable transmission and timely delivery of EMs. From the results, it is evident that the CSFD protocol significantly improves the performance compared to SDN. While lowering the average end-to-end delay and packet dropping ratio by 26.35 and 21.09%, respectively, the goodput, throughput, and packet delivery ratio are enhanced by 26.353, 5.277, and 5.27%.

This paper demonstrates the device-circuit co-design of a novel non-volatile latch utilizing 20 nm channel length silicon-on-insulator (SOI) based junctionless (JL) ferroelectric field effect transistor (FEFET). Through a combination of experimentally calibrated models and TCAD-based mixed-mode simulations, JL FEFET memory devices are shown to be effective in non-volatile latch applications. Firstly, a device-level performance assessment is carried out to obtain the programming speed, data retention, and endurance. The results demonstrate the potential of 20 nm channel length JL FEFET for non-volatile logic-in-memory applications, showcasing their ability to provide higher memory density, improved scalability, and reduced power consumption compared to conventional memory technologies. Herein, junctionless ferroelectric field effect transistor with a Metal-Ferroelectric-Insulator-Semiconductor gate stack of a 10 nm Hf_0.4Zr_0.6O₂ (HZO) thickness is demonstrated, which attains a memory window of 0.9 V. This paper further investigates JL FEFET-based novel non-volatile latch, which has an automatic load-store mechanism.