An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2023-12-20 DOI:10.1109/LSSC.2023.3344699
Qirui Zhang;Hyochan An;Andrea Bejarano-Carbo;Hun-Seok Kim;David Blaauw;Dennis Sylvester
{"title":"An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems","authors":"Qirui Zhang;Hyochan An;Andrea Bejarano-Carbo;Hun-Seok Kim;David Blaauw;Dennis Sylvester","doi":"10.1109/LSSC.2023.3344699","DOIUrl":null,"url":null,"abstract":"This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by \n<inline-formula> <tex-math>$2.6\\times $ </tex-math></inline-formula>\n at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only \n<inline-formula> <tex-math>$1.21 {\\mu }\\text{W}$ </tex-math></inline-formula>\n, with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings \n<inline-formula> <tex-math>$133\\times $ </tex-math></inline-formula>\n reduction to the overall energy for regressing an image of change-detected region of interest.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10366504/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by $2.6\times $ at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only $1.21 {\mu }\text{W}$ , with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings $133\times $ reduction to the overall energy for regressing an image of change-detected region of interest.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于智能事件驱动物联网成像系统的超低功耗 H.264/AVC 帧内图像压缩加速器
本文介绍了一种超低功耗(ULP)H.264/AVC 帧内图像压缩加速器,它是为智能事件驱动的 ULP 物联网成像系统量身定制的。H.264/AVC 帧内编解码器经过定制,能够压缩任意非矩形变化检测区域。为了优化图像内存访问的能耗和延迟,为帧内预测提出了新的算法-硬件协同设计,在质量损失可忽略不计的情况下,将相邻宏块(McB)访问的开销降低了2.6美元/次。通过对主要处理阶段的分割控制,利用数据依赖性和流水线优化了延迟。通过数据路径微架构重新配置,减少了主要计算单元的面积和泄漏。该芯片采用 40 纳米制造工艺,占地面积仅为 0.32 平方毫米,配备 4KB SRAM。在 0.6 V 和 153 kHz 条件下,其能耗仅为 1.21 {\mu }text{W}$,压缩能效为 30.9 pJ/像素,可与最先进的设计相媲美。对于事件驱动的物联网成像系统而言,将所提出的加速器与变化检测相结合,可使对变化检测到的感兴趣区域的图像进行回归时的总能耗降低 133 倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
期刊最新文献
0.6-V, μW-Power Four-Stage OTA With Minimal Components, and 100× Load Range Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler A 12 V Compliant Multichannel Dual Mode Neural Stimulator With 0.004% Charge Mismatch and a 4×VDD Tolerant On-Chip Discharge Switch in Low-Voltage CMOS A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator S2D-CIM: SRAM-Based Systolic Digital Compute-in-Memory Framework With Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1