Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process

Abstract

In this manuscript, a low noise amplifier (LNA) circuit with low power consumption of 5.3 mW for 3–12 GHz ultra-wideband (UWB) is designed in 90 nm standard CMOS process. A noise-canceling (NC) approach consisting of both common-gate (CG) and common-source (CS) as input stage, followed by the g_m-boosted current-reused stage to enhance the gain performance, is used in the proposed design. After noise-canceling, the achieved noise-figure (NF) is ranging from 2.28 to 3.55 dB for 3.1–10.6 GHz and a maximum of 4.0 dB at 12 GHz. Input-reflection coefficient (S₁₁) of < −12.57 dB is achieved from this CG-CS input-matching stage. With the use of parallel-series LC matching with series-peaking-inductor followed by the g_m-boosting stage improves the gain-bandwidth and delivers a flat power-gain (S₂₁) of 18.33 ± 0.76 dB over 3–12 GHz. The CG configuration at the input side provides a high reverse-isolation (S₁₂) of less than −78.23 dB and common-drain configuration with NMOS load at the output side ensures less than −11.79 dB output-reflection coefficient (S₂₂) over the proposed frequency range. The proposed LNA is operated with 0.7 V V_dd and the achieved intercept points for input (IIP3) and output (OIP3) are −11.1 dBm and +6.2 dBm, respectively.