Pub Date : 2024-11-19DOI: 10.1016/j.vlsi.2024.102307
Jie Zhang, Nana Cheng, Jiangang Zuo, Pengyuan Wang, Xiaodong Wei
A new four-dimensional memristor conservative chaotic system (MCCS) is constructed by introducing a sine magnetic memristor into the Sprott-A system in this paper. Through the analysis of the dynamic behavior of the MCCS, it is found that the system is a non-Hamiltonian chaotic system, exhibiting continuous chaotic intervals and high complexity. At the same time, a series of special phenomena have been observed in MCCS, such as multiple stability, parameter-controllable multi-scrolls, bursty oscillations, and distinctive spike oscillations. Additionally, the correctness of the mathematical model of the MCCS is confirmed through analog and FPGA digital circuit. Finally, a synchronous encryption system with strong attack resistance is designed by combining MCCS with RNA algorithm.
{"title":"Design, analysis and application of Non-Hamiltonian conservative chaotic system based on memristor","authors":"Jie Zhang, Nana Cheng, Jiangang Zuo, Pengyuan Wang, Xiaodong Wei","doi":"10.1016/j.vlsi.2024.102307","DOIUrl":"10.1016/j.vlsi.2024.102307","url":null,"abstract":"<div><div>A new four-dimensional memristor conservative chaotic system (MCCS) is constructed by introducing a sine magnetic memristor into the Sprott-A system in this paper. Through the analysis of the dynamic behavior of the MCCS, it is found that the system is a non-Hamiltonian chaotic system, exhibiting continuous chaotic intervals and high complexity. At the same time, a series of special phenomena have been observed in MCCS, such as multiple stability, parameter-controllable multi-scrolls, bursty oscillations, and distinctive spike oscillations. Additionally, the correctness of the mathematical model of the MCCS is confirmed through analog and FPGA digital circuit. Finally, a synchronous encryption system with strong attack resistance is designed by combining MCCS with RNA algorithm.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102307"},"PeriodicalIF":2.2,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142698861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-16DOI: 10.1016/j.vlsi.2024.102306
Yupei Yang , Cong Wang , Hongli Zhang , Ping Ma , Yue Meng , Shaohua Zhang
In the field of secure communication, chaotic synchronization plays a vital role, while fixed-time synchronization has realistic application prospects and needs. For the synchronization problem of complex chaotic systems containing unknown parameters and perturbations in the complex domain, a fixed-time cross-combination synchronization method based on a novel adaptive sliding mode control is proposed. The scheme takes three complex chaotic driving systems and one complex chaotic response system containing unknown parameters and perturbations as the research objects, and firstly, the synchronization controller and parameter updating law are designed based on the adaptive rate and fixed-time stability theory to realize the synchronization of the system and the identification of the unknown parameters, and the feasibility of the scheme is verified by the detailed Lyapunov stability theory analysis. Subsequently, four classical complex chaotic systems with universality are selected for model analysis and synchronization scheme design, and numerical simulations are carried out. The feasibility and superiority of the scheme are verified by comparison experiments with the conventional finite-time synchronization scheme and robustness experiments. In this study, adaptive sliding mode control is combined with fixed-time combinatorial synchronization of complex-domain chaotic systems, and a cross-combination strategy is introduced to enhance the safety and anti-interference ability of the system. This not only theoretically expands the application of control theory to the combinatorial synchronization problem of complex systems, but also significantly enhances the stability and reliability of the system under uncertainty and disturbance environments.
{"title":"Fixed-time cross-combination synchronization of complex chaotic systems with unknown parameters and perturbations","authors":"Yupei Yang , Cong Wang , Hongli Zhang , Ping Ma , Yue Meng , Shaohua Zhang","doi":"10.1016/j.vlsi.2024.102306","DOIUrl":"10.1016/j.vlsi.2024.102306","url":null,"abstract":"<div><div>In the field of secure communication, chaotic synchronization plays a vital role, while fixed-time synchronization has realistic application prospects and needs. For the synchronization problem of complex chaotic systems containing unknown parameters and perturbations in the complex domain, a fixed-time cross-combination synchronization method based on a novel adaptive sliding mode control is proposed. The scheme takes three complex chaotic driving systems and one complex chaotic response system containing unknown parameters and perturbations as the research objects, and firstly, the synchronization controller and parameter updating law are designed based on the adaptive rate and fixed-time stability theory to realize the synchronization of the system and the identification of the unknown parameters, and the feasibility of the scheme is verified by the detailed Lyapunov stability theory analysis. Subsequently, four classical complex chaotic systems with universality are selected for model analysis and synchronization scheme design, and numerical simulations are carried out. The feasibility and superiority of the scheme are verified by comparison experiments with the conventional finite-time synchronization scheme and robustness experiments. In this study, adaptive sliding mode control is combined with fixed-time combinatorial synchronization of complex-domain chaotic systems, and a cross-combination strategy is introduced to enhance the safety and anti-interference ability of the system. This not only theoretically expands the application of control theory to the combinatorial synchronization problem of complex systems, but also significantly enhances the stability and reliability of the system under uncertainty and disturbance environments.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102306"},"PeriodicalIF":2.2,"publicationDate":"2024-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142698000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a PE-based parallelism configurable polar encoder hardware architecture for emerging high-speed 5G communication system. This encoder architecture is applied to the 5G-NR PBCH channel polar encoder, implemented with functional modules such as CRC generation and interleaving, channel encoding, and rate matching as specified in the 3GPP protocol. Next, based on the united power format (UPF) low-power management technology, the PBCH polar encoder architecture is divided into different power domains based on their operating characteristics to reduce the power consumption. Experimental results show that the proposed polar encoder achieves throughput up to 30 Gbps. Based on TSMC 40 nm CMOS technology, by applying the proposed low-power methodology, the power consumption of the PBCH polar encoder at parallelisms of 8, 16, and 32 are 1.236 , 1.170 , and 1.084 , achieving power reductions of 24%, 29%, and 35% when comparing to non-low-power design, respectively.
{"title":"PE-based high throughput and low power polar encoder for 5G-NR PBCH channel","authors":"Zhiyi Zeng , Haiyu Xiao , Shida Zhong , Peichang Zhang , Tao Yuan , Yu-hang Xiao","doi":"10.1016/j.vlsi.2024.102303","DOIUrl":"10.1016/j.vlsi.2024.102303","url":null,"abstract":"<div><div>In this paper, we propose a PE-based parallelism configurable polar encoder hardware architecture for emerging high-speed 5G communication system. This encoder architecture is applied to the 5G-NR PBCH channel polar encoder, implemented with functional modules such as CRC generation and interleaving, channel encoding, and rate matching as specified in the 3GPP protocol. Next, based on the united power format (UPF) low-power management technology, the PBCH polar encoder architecture is divided into different power domains based on their operating characteristics to reduce the power consumption. Experimental results show that the proposed polar encoder achieves throughput up to 30 Gbps. Based on TSMC 40 nm CMOS technology, by applying the proposed low-power methodology, the power consumption of the PBCH polar encoder at parallelisms of 8, 16, and 32 are 1.236 <span><math><mi>mW</mi></math></span>, 1.170 <span><math><mi>mW</mi></math></span>, and 1.084 <span><math><mi>mW</mi></math></span>, achieving power reductions of 24%, 29%, and 35% when comparing to non-low-power design, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102303"},"PeriodicalIF":2.2,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142652124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
True random number generators (TRNGs) perform an extremely critical role in cryptographic algorithms and security protocols, scientific simulation, industrial testing, privacy protection, and numerous other domains. Nevertheless, modern TRNGs have difficulty striking a reasonable balance between high throughput and low hardware consumption. In this paper, a novel lightweight high-throughput TRNG based on state switchable ring oscillators (SSROs) is proposed. Under the effect of flip-flops that are prone to entering the metastable region, the SSROs randomly switch between oscillatory and buffer states to create jitter and metastability. A feedback strategy is adopted to effectively eliminate the fixed point in the circuit, which further enhances the randomness of the structure. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs, with support for automatic routing. It achieves a throughput of up to 400 Mbps while consuming only 16 LUTs and 13 DFFs, showing extremely high resource utilization efficiency. Experimental results show that the output random sequence passes the NIST SP800-22 test, the NIST SP800-90B test, and the AIS-31 test without any post-processing, exhibiting strong robustness against voltage and temperature variations as well as frequency injection attacks.
{"title":"Lightweight high-throughput true random number generator based on state switchable ring oscillator","authors":"Shehui Wu, Huaguo Liang, Siyu Wang, Hao Lv, Maoxiang Yi, Yingchun Lu","doi":"10.1016/j.vlsi.2024.102305","DOIUrl":"10.1016/j.vlsi.2024.102305","url":null,"abstract":"<div><div>True random number generators (TRNGs) perform an extremely critical role in cryptographic algorithms and security protocols, scientific simulation, industrial testing, privacy protection, and numerous other domains. Nevertheless, modern TRNGs have difficulty striking a reasonable balance between high throughput and low hardware consumption. In this paper, a novel lightweight high-throughput TRNG based on state switchable ring oscillators (SSROs) is proposed. Under the effect of flip-flops that are prone to entering the metastable region, the SSROs randomly switch between oscillatory and buffer states to create jitter and metastability. A feedback strategy is adopted to effectively eliminate the fixed point in the circuit, which further enhances the randomness of the structure. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs, with support for automatic routing. It achieves a throughput of up to 400 Mbps while consuming only 16 LUTs and 13 DFFs, showing extremely high resource utilization efficiency. Experimental results show that the output random sequence passes the NIST SP800-22 test, the NIST SP800-90B test, and the AIS-31 test without any post-processing, exhibiting strong robustness against voltage and temperature variations as well as frequency injection attacks.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102305"},"PeriodicalIF":2.2,"publicationDate":"2024-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142652125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-06DOI: 10.1016/j.vlsi.2024.102304
Shuoshuo Zhu, Bin Wang, Xiaokun Lin, Lu Liu, Xiao Qu, Weitao Yang
This paper presents a low-noise instrument amplifier (LNA) for neural signal acquisition. The proposed LNA consists of two operational transconductance amplifiers (OTA), feedback loops, a positive feedback loop (PFL), a DC servo loop (DSL) and the internal chopper switch located between the capacitive feedback loop and op-amp. The LNA employs the capacitively coupled amplifier with the internal chopper to obtain the rail to rail electrode dc offset (EDO) rejection ability and eliminate the flicker noise of OTA. The PFL is designed to improve the input impedance of the circuit, and the DSL is introduced to suppress the residual offset introduced by the chopper switch. Realized in a 40 nm CMOS technology with 0.69 × 0.1 mm2, the LNA draws 7.4 μA from a supply voltage of 2.5Vand exhibits 1.69 μVrms input-referred noise (IRN) over 1–200 Hz for low frequency and low amplitude neural signals. Besides, the simulation results show that the LNA achieves 87.12 dB common-mode rejection ratio (CMRR), 87.64 dB power-supply rejection ratio (PSRR) and 2.75 GΩ input impedance at 50 Hz.
{"title":"A low noise instrument amplifier in 40 nm CMOS with positive feedback loop and DC servo loop for neural signal acquisition","authors":"Shuoshuo Zhu, Bin Wang, Xiaokun Lin, Lu Liu, Xiao Qu, Weitao Yang","doi":"10.1016/j.vlsi.2024.102304","DOIUrl":"10.1016/j.vlsi.2024.102304","url":null,"abstract":"<div><div>This paper presents a low-noise instrument amplifier (LNA) for neural signal acquisition. The proposed LNA consists of two operational transconductance amplifiers (OTA), feedback loops, a positive feedback loop (PFL), a DC servo loop (DSL) and the internal chopper switch located between the capacitive feedback loop and op-amp. The LNA employs the capacitively coupled amplifier with the internal chopper to obtain the rail to rail electrode dc offset (EDO) rejection ability and eliminate the flicker noise of OTA. The PFL is designed to improve the input impedance of the circuit, and the DSL is introduced to suppress the residual offset introduced by the chopper switch. Realized in a 40 nm CMOS technology with 0.69 × 0.1 mm<sup>2</sup>, the LNA draws 7.4 μA from a supply voltage of 2.5Vand exhibits 1.69 μVrms input-referred noise (IRN) over 1–200 Hz for low frequency and low amplitude neural signals. Besides, the simulation results show that the LNA achieves 87.12 dB common-mode rejection ratio (CMRR), 87.64 dB power-supply rejection ratio (PSRR) and 2.75 GΩ input impedance at 50 Hz.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102304"},"PeriodicalIF":2.2,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142652159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-05DOI: 10.1016/j.vlsi.2024.102302
Yafei Cao, Hongjun Liu
Key expansion is an essential component in block cryptography, which serves the round function. By analyzing key expansion module of AES, it is found that the round-keys are highly correlated, and current round-key can be derived from its previous or the next round-key. To address these weaknesses, first, a 2D exponential chaotic map (2D-ECM) that exhibits ergodicity and superior randomness was constructed. Then, the Lyapunov exponents (LEs) were calculated based on the singular value decomposition (SVD) method. In addition, TestU01 test results showed that the sequences generated by 2D-ECM have better randomness. Further, an enhanced key expansion module was designed utilizing 2D-ECM and primitive polynomial over GF(2n), which has irreversibility and parallelism, and the round-keys are independent of each other. Simulation results and performance analysis demonstrated the effectiveness of the proposed enhanced key expansion module.
{"title":"An enhanced key expansion module based on 2D hyper chaotic map and Galois field","authors":"Yafei Cao, Hongjun Liu","doi":"10.1016/j.vlsi.2024.102302","DOIUrl":"10.1016/j.vlsi.2024.102302","url":null,"abstract":"<div><div>Key expansion is an essential component in block cryptography, which serves the round function. By analyzing key expansion module of AES, it is found that the round-keys are highly correlated, and current round-key can be derived from its previous or the next round-key. To address these weaknesses, first, a 2D exponential chaotic map (2D-ECM) that exhibits ergodicity and superior randomness was constructed. Then, the Lyapunov exponents (LEs) were calculated based on the singular value decomposition (SVD) method. In addition, TestU01 test results showed that the sequences generated by 2D-ECM have better randomness. Further, an enhanced key expansion module was designed utilizing 2D-ECM and primitive polynomial over GF(2<sup><em>n</em></sup>), which has irreversibility and parallelism, and the round-keys are independent of each other. Simulation results and performance analysis demonstrated the effectiveness of the proposed enhanced key expansion module.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102302"},"PeriodicalIF":2.2,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142652158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-05DOI: 10.1016/j.vlsi.2024.102301
You Lü , Qiang Lai , Jianning Huang
The exploration of memristive chaotic systems (MCSs) has been a prominent area of research due to the inherent richness of their dynamical characteristics. The objective of this paper is to propose two chaotic systems, derived from a common basic system, which also exhibit distinct characteristics such as coexisting attractors and robustness of chaos while maintaining the common attributes of multi-parameter amplitude modulation and large-scale offset boosting. The evolution process of MCSs' dynamical behavior with changes to parameters and initial values is described in detail through the analysis of bifurcation diagrams, Lyapunov exponents (LEs), and phase projections. Furthermore, the findings of the numerical simulations are validated by circuit implementations, thereby providing additional confirmation of the existence of the two memristive chaotic systems constructed and their potential for practical applications.
{"title":"Simple memristive chaotic systems with complex dynamics","authors":"You Lü , Qiang Lai , Jianning Huang","doi":"10.1016/j.vlsi.2024.102301","DOIUrl":"10.1016/j.vlsi.2024.102301","url":null,"abstract":"<div><div>The exploration of memristive chaotic systems (MCSs) has been a prominent area of research due to the inherent richness of their dynamical characteristics. The objective of this paper is to propose two chaotic systems, derived from a common basic system, which also exhibit distinct characteristics such as coexisting attractors and robustness of chaos while maintaining the common attributes of multi-parameter amplitude modulation and large-scale offset boosting. The evolution process of MCSs' dynamical behavior with changes to parameters and initial values is described in detail through the analysis of bifurcation diagrams, Lyapunov exponents (LEs), and phase projections. Furthermore, the findings of the numerical simulations are validated by circuit implementations, thereby providing additional confirmation of the existence of the two memristive chaotic systems constructed and their potential for practical applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102301"},"PeriodicalIF":2.2,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142592936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-20DOI: 10.1016/j.vlsi.2024.102299
Xiaotian Guo , Quan Jiang , Andy D. Pimentel , Todor Stefanov
Prevalent large CNN models pose a significant challenge in terms of computing resources for resource-constrained devices at the Edge. Distributing the computations and coefficients over multiple edge devices collaboratively has been well studied but these works generally do not consider the presence of device failures (e.g., due to temporary connectivity issues, overload, discharged battery of edge devices). Such unpredictable failures can compromise the reliability of edge devices, inhibiting the proper execution of distributed CNN inference. In this paper, we present a novel partitioning method, called RobustDiCE, for robust distribution and inference of CNN models over multiple edge devices. Our method can tolerate intermittent and permanent device failures in a distributed system at the Edge, offering a tunable trade-off between robustness (i.e., retaining model accuracy after failures) and resource utilization. We verify the system’s robustness by validating the overall end-to-end latency under failures. We evaluate RobustDiCE using the ImageNet-1K dataset on several representative CNN models under various device failure scenarios and compare it with several state-of-the-art partitioning methods as well as an optimal robustness approach (i.e., full neuron replication). In addition, we demonstrate RobustDiCE’s advantages in terms of memory usage and energy consumption per device, and system throughput for various system setups with different device counts.
{"title":"Model and system robustness in distributed CNN inference at the edge","authors":"Xiaotian Guo , Quan Jiang , Andy D. Pimentel , Todor Stefanov","doi":"10.1016/j.vlsi.2024.102299","DOIUrl":"10.1016/j.vlsi.2024.102299","url":null,"abstract":"<div><div>Prevalent large CNN models pose a significant challenge in terms of computing resources for resource-constrained devices at the Edge. Distributing the computations and coefficients over multiple edge devices collaboratively has been well studied but these works generally do not consider the presence of device failures (e.g., due to temporary connectivity issues, overload, discharged battery of edge devices). Such unpredictable failures can compromise the reliability of edge devices, inhibiting the proper execution of distributed CNN inference. In this paper, we present a novel partitioning method, called RobustDiCE, for robust distribution and inference of CNN models over multiple edge devices. Our method can tolerate intermittent and permanent device failures in a distributed system at the Edge, offering a tunable trade-off between robustness (i.e., retaining model accuracy after failures) and resource utilization. We verify the system’s robustness by validating the overall end-to-end latency under failures. We evaluate RobustDiCE using the ImageNet-1K dataset on several representative CNN models under various device failure scenarios and compare it with several state-of-the-art partitioning methods as well as an optimal robustness approach (i.e., full neuron replication). In addition, we demonstrate RobustDiCE’s advantages in terms of memory usage and energy consumption per device, and system throughput for various system setups with different device counts.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102299"},"PeriodicalIF":2.2,"publicationDate":"2024-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142530090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-19DOI: 10.1016/j.vlsi.2024.102300
Yugal Kishore Maheshwari, Manoj Sachdev
Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively.
触发器（FF）是数字电路的重要组成部分，但其功耗和能耗却很高。本文介绍了 VLFF，一种仅使用两个单相时钟晶体管运行的超低功耗触发器。提取的仿真结果表明，在 0% 至 45% 的数据活动（DA）范围内，VLFF 是所有受检 FF 中最省电的 FF。采用 TSMC CMOS 65 nm gp PDK 设计的测试芯片测量结果表明，在 VDD = 1 V 时，与 TGFF 和 18TSPC 相比，12.5% DA 的功耗分别降低了 63% 和 16%，25% DA 的功耗分别降低了 52% 和 6%。
{"title":"VLFF — A very low-power flip-flop with only two clock transistors","authors":"Yugal Kishore Maheshwari, Manoj Sachdev","doi":"10.1016/j.vlsi.2024.102300","DOIUrl":"10.1016/j.vlsi.2024.102300","url":null,"abstract":"<div><div>Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102300"},"PeriodicalIF":2.2,"publicationDate":"2024-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142530088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-13DOI: 10.1016/j.vlsi.2024.102298
Salam J. Yaqoob , Salah Kamel , Francisco Jurado , Saad Motahhir , Abdelilah Chalh , Husam Arnoos
This paper presents an effective approach to achieve maximum power point tracking (MPPT) in photovoltaic (PV) systems for battery charging using a single-sensor incremental conductance (InC) method. The objective is to optimize the MPPT process while minimizing the number of sensors required. The suggested technique leverages the relationship between the PV module's output voltage and the duty cycle to automatically adjust and reach the MPP, resulting in optimal power generation. By eliminating the PV current sensor from the control circuit, the developed method reduces both the cost and size of the MPPT circuit. Compared to the conventional InC method, the developed approach demonstrates improved response speed and accuracy in steady-state operation, along with the ability to damp oscillations near the MPP. Extensive simulations using MATLAB/Simulink validate the performance of the developed technique across various environmental conditions. The results highlight the recommended method's realistic and effective MPP tracking capabilities, achieving higher efficiency (99.12 %) compared to the classical method (97.8 %) under high irradiance levels.
{"title":"Efficient and cost-effective maximum power point tracking technique for solar photovoltaic systems with Li-ion battery charging","authors":"Salam J. Yaqoob , Salah Kamel , Francisco Jurado , Saad Motahhir , Abdelilah Chalh , Husam Arnoos","doi":"10.1016/j.vlsi.2024.102298","DOIUrl":"10.1016/j.vlsi.2024.102298","url":null,"abstract":"<div><div>This paper presents an effective approach to achieve maximum power point tracking (MPPT) in photovoltaic (PV) systems for battery charging using a single-sensor incremental conductance (InC) method. The objective is to optimize the MPPT process while minimizing the number of sensors required. The suggested technique leverages the relationship between the PV module's output voltage and the duty cycle to automatically adjust and reach the MPP, resulting in optimal power generation. By eliminating the PV current sensor from the control circuit, the developed method reduces both the cost and size of the MPPT circuit. Compared to the conventional InC method, the developed approach demonstrates improved response speed and accuracy in steady-state operation, along with the ability to damp oscillations near the MPP. Extensive simulations using MATLAB/Simulink validate the performance of the developed technique across various environmental conditions. The results highlight the recommended method's realistic and effective MPP tracking capabilities, achieving higher efficiency (99.12 %) compared to the classical method (97.8 %) under high irradiance levels.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102298"},"PeriodicalIF":2.2,"publicationDate":"2024-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142440874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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