Pub Date : 2025-02-19DOI: 10.1016/j.vlsi.2025.102387
JiaXin Tang , YaLian Wu , ChunYuan Ou , Pengcheng Zhong , Xue Zhao , Minglin Ma
The functional network of the human brain exhibits scale-free topology, and there are inevitable time delays in information transmission between neurons. This study explores the relationship between synchronization transitions and heterogeneous time delays in scale-free neuronal networks, as well as the influence of coupling strength on the synchronization process under the premise of introducing heterogeneous time delays. Inspired by small-world network construction methods, we designed a scale-free neural network model with heterogeneous time delays based on the Rulkov neuron model, referred to as the Heterogeneous Scale-Free Neural Network (HSFNN). In this paper, we propose a time delay determination mechanism (TDDM). Subsequently, we conducted numerical simulations to analyze the effects of various parameters related to time delays on the synchronization of HSFNNs. The results were analyzed using spatiotemporal state diagrams, recursion diagrams, and node state diagrams. The findings indicate that HSFNNs exhibit various dynamical phenomena, such as asynchronous, synchronous, and alternating states of synchronization and asynchrony. Furthermore, we found that altering coupling strength under the premise of introducing heterogeneous time delays also affects the synchronization states of HSFNNs.
{"title":"Synchronization in scale-free neural networks with heterogeneous time delay","authors":"JiaXin Tang , YaLian Wu , ChunYuan Ou , Pengcheng Zhong , Xue Zhao , Minglin Ma","doi":"10.1016/j.vlsi.2025.102387","DOIUrl":"10.1016/j.vlsi.2025.102387","url":null,"abstract":"<div><div>The functional network of the human brain exhibits scale-free topology, and there are inevitable time delays in information transmission between neurons. This study explores the relationship between synchronization transitions and heterogeneous time delays in scale-free neuronal networks, as well as the influence of coupling strength on the synchronization process under the premise of introducing heterogeneous time delays. Inspired by small-world network construction methods, we designed a scale-free neural network model with heterogeneous time delays based on the Rulkov neuron model, referred to as the Heterogeneous Scale-Free Neural Network (HSFNN). In this paper, we propose a time delay determination mechanism (TDDM). Subsequently, we conducted numerical simulations to analyze the effects of various parameters related to time delays on the synchronization of HSFNNs. The results were analyzed using spatiotemporal state diagrams, recursion diagrams, and node state diagrams. The findings indicate that HSFNNs exhibit various dynamical phenomena, such as asynchronous, synchronous, and alternating states of synchronization and asynchrony. Furthermore, we found that altering coupling strength under the premise of introducing heterogeneous time delays also affects the synchronization states of HSFNNs.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102387"},"PeriodicalIF":2.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143471531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-19DOI: 10.1016/j.vlsi.2025.102381
Hari Krishna Kharidu, V. Sudha
This paper has presented a new electroencephalogram (EEG)-based encryption technique for enhancing image data security using an FPGA implementation for IoT applications. The technique has used EEG datasets to create 64-bit keys, which have undergone testing using the NIST SP 800-22 test suite for randomness check. The generated keys have been combined with the image data and subjected to substitution and LFSR-based permutation in a proposed order. The proposed method has implemented the RTL design on a Virtex-7 FPGA device, with careful selection of rounds to optimize encryption process efficiency. The hardware expenditure per round on the FPGA device has been assessed to determine the optimal limit on the number of rounds, and the simulation results have been validated using MATLAB. The parameters Number of Changing Pixel Rate (NPCR) and Unified Averaged Changed Intensity (UACI) have been calculated as 99.5697% and 33.4776%, respectively, while the entropy of the encrypted image is 7.95, indicating that the suggested approach exhibits greater resilience against differential attacks. The proposed method has achieved a maximum operating frequency of 815.395 MHz and efficiency of 5.623 Mbps/slice on Virtex-7 FPGA device which has exhibited a 49.95% increase in the maximum frequency of operation and a 7.11% gain in efficiency when compared with the state of the art. These improvements have been important for reducing the encryption time and efficiently utilizing the hardware with the optimum number of slices.
{"title":"FPGA implementation of EEG based hardware optimized data encryption technique for IoT applications","authors":"Hari Krishna Kharidu, V. Sudha","doi":"10.1016/j.vlsi.2025.102381","DOIUrl":"10.1016/j.vlsi.2025.102381","url":null,"abstract":"<div><div>This paper has presented a new electroencephalogram (EEG)-based encryption technique for enhancing image data security using an FPGA implementation for IoT applications. The technique has used EEG datasets to create 64-bit keys, which have undergone testing using the NIST SP 800-22 test suite for randomness check. The generated keys have been combined with the image data and subjected to substitution and LFSR-based permutation in a proposed order. The proposed method has implemented the RTL design on a Virtex-7 FPGA device, with careful selection of rounds to optimize encryption process efficiency. The hardware expenditure per round on the FPGA device has been assessed to determine the optimal limit on the number of rounds, and the simulation results have been validated using MATLAB. The parameters Number of Changing Pixel Rate (NPCR) and Unified Averaged Changed Intensity (UACI) have been calculated as 99.5697% and 33.4776%, respectively, while the entropy of the encrypted image is 7.95, indicating that the suggested approach exhibits greater resilience against differential attacks. The proposed method has achieved a maximum operating frequency of 815.395 MHz and efficiency of 5.623 Mbps/slice on Virtex-7 FPGA device which has exhibited a 49.95% increase in the maximum frequency of operation and a 7.11% gain in efficiency when compared with the state of the art. These improvements have been important for reducing the encryption time and efficiently utilizing the hardware with the optimum number of slices.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102381"},"PeriodicalIF":2.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143473998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-12DOI: 10.1016/j.vlsi.2025.102347
Zahra Shirmohammadi, Masoumeh Taali
Interposer-based multi-chip Deep Learning Accelerator (DLA) profoundly influences the design of artificial intelligence (AI) hardware. However, data transmission over wires in Network-on-Chip (NoC)-based Deep Learning Accelerators (DLAs) encounters crosstalk faults as a major challenge. These faults arise due to mutual capacitance and inductance influences between adjacent wires of the NoCs. To address this issue, this paper introduces JoBiS, a bit-stuffing algorithm that takes into account both capacitance and inductance coupling effects. JoBiS aims to prevent the occurrence of the worst delay transitions in inductance coupling, such as 0000000000, and 00-0011-11, as well as in capacitive coupling, including 11-1100-00, 0101010101, and 1010101010, in a 5-bit wire model. This is achieved through a simple and low-power algorithm. To reduce delay and area overhead in large buses, a bus partitioning-based CAC called JoBiS is proposed. The simulation results indicate that the power consumption and delay are significantly improved compared to other methods. On average, JoBiS reduces power consumption and critical path delay by 83% and 70%, respectively, across various bus widths.
{"title":"JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator","authors":"Zahra Shirmohammadi, Masoumeh Taali","doi":"10.1016/j.vlsi.2025.102347","DOIUrl":"10.1016/j.vlsi.2025.102347","url":null,"abstract":"<div><div>Interposer-based multi-chip Deep Learning Accelerator (DLA) profoundly influences the design of artificial intelligence (AI) hardware. However, data transmission over wires in Network-on-Chip (NoC)-based Deep Learning Accelerators (DLAs) encounters crosstalk faults as a major challenge. These faults arise due to mutual capacitance and inductance influences between adjacent wires of the NoCs. To address this issue, this paper introduces JoBiS, a bit-stuffing algorithm that takes into account both capacitance and inductance coupling effects. JoBiS aims to prevent the occurrence of the worst delay transitions in inductance coupling, such as 00000<span><math><mrow><mo>→</mo><mn>11111</mn><mo>,</mo><mn>11111</mn><mo>→</mo></mrow></math></span>00000, and 00-00<span><math><mo>→</mo></math></span>11-11, as well as in capacitive coupling, including 11-11<span><math><mo>→</mo></math></span>00-00, 01010<span><math><mo>→</mo></math></span>10101, and 10101<span><math><mo>→</mo></math></span>01010, in a 5-bit wire model. This is achieved through a simple and low-power algorithm. To reduce delay and area overhead in large buses, a bus partitioning-based CAC called JoBiS is proposed. The simulation results indicate that the power consumption and delay are significantly improved compared to other methods. On average, JoBiS reduces power consumption and critical path delay by 83% and 70%, respectively, across various bus widths.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102347"},"PeriodicalIF":2.2,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143395413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-11DOI: 10.1016/j.vlsi.2025.102382
Jiayi Wang , Yichen Zhang , Yuanjun Guan , Tao Wang , Qianchuan Yi , Wenxin Jiang , Xiaopu Gu , Li Zhang , Binbing Huang , Tianyan Han , Lilei Hu
In the realm of high-energy particle detection, a trade-off exists between achieving a large sensitive area and ensuring high-speed detector response. Current methodologies, such as negative Miller capacitance, have made progress in enhancing both detection area and response speed. Nevertheless, these designs frequently suffer from limitations in parasitic capacitance, especially with large detection areas, which ultimately constrains bandwidth. This study introduces a segmented-integration method combined with optimized front-end circuits to overcome these challenges. By segmenting a single large sensitive area into smaller pixels, each coupled with an independent front-end transimpedance amplifier (TIA), this design can significantly enhance the response speed while maintaining a large sensitive area. Although it complicates the overall system, the output signals from each pixel are summed to preserve the detector's large-area capability. This study has developed novel front-end circuits for both linear and Geiger modes, offering exceptional performance in terms of detector gain and bandwidth. In linear mode, a multi-channel TIA is designed to handle up to 32 pixels simultaneously, providing a gain of 50 dBΩ and 450 MHz bandwidth despite 160 pF parasitic capacitance. For Geiger mode, a novel TIA with a feedforward is proposed, providing a gain of 70 dBΩ and 450 MHz bandwidth for a pixel with a 5 pF parasitic capacitance without the need for compensating capacitors. To enable rapid single-particle counting, a four-delay trigger sampling comparator structure is designed with a sampling rate reaching 4 GS/s under process limitation. The circuits are designed in 180 nm CMOS process and verified through Sentaurus and Cadence simulation software, demonstrating excellent performance with a 68.8 mm2 detection area and an ultrahigh cutoff frequency of 450 MHz.
{"title":"Transimpedance amplifiers for large-area and ultrahigh bandwidth high-energy particle detectors","authors":"Jiayi Wang , Yichen Zhang , Yuanjun Guan , Tao Wang , Qianchuan Yi , Wenxin Jiang , Xiaopu Gu , Li Zhang , Binbing Huang , Tianyan Han , Lilei Hu","doi":"10.1016/j.vlsi.2025.102382","DOIUrl":"10.1016/j.vlsi.2025.102382","url":null,"abstract":"<div><div>In the realm of high-energy particle detection, a trade-off exists between achieving a large sensitive area and ensuring high-speed detector response. Current methodologies, such as negative Miller capacitance, have made progress in enhancing both detection area and response speed. Nevertheless, these designs frequently suffer from limitations in parasitic capacitance, especially with large detection areas, which ultimately constrains bandwidth. This study introduces a segmented-integration method combined with optimized front-end circuits to overcome these challenges. By segmenting a single large sensitive area into smaller pixels, each coupled with an independent front-end transimpedance amplifier (TIA), this design can significantly enhance the response speed while maintaining a large sensitive area. Although it complicates the overall system, the output signals from each pixel are summed to preserve the detector's large-area capability. This study has developed novel front-end circuits for both linear and Geiger modes, offering exceptional performance in terms of detector gain and bandwidth. In linear mode, a multi-channel TIA is designed to handle up to 32 pixels simultaneously, providing a gain of 50 dBΩ and 450 MHz bandwidth despite 160 pF parasitic capacitance. For Geiger mode, a novel TIA with a feedforward is proposed, providing a gain of 70 dBΩ and 450 MHz bandwidth for a pixel with a 5 pF parasitic capacitance without the need for compensating capacitors. To enable rapid single-particle counting, a four-delay trigger sampling comparator structure is designed with a sampling rate reaching 4 GS/s under process limitation. The circuits are designed in 180 nm CMOS process and verified through Sentaurus and Cadence simulation software, demonstrating excellent performance with a 68.8 mm<sup>2</sup> detection area and an ultrahigh cutoff frequency of 450 MHz.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102382"},"PeriodicalIF":2.2,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143445044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-08DOI: 10.1016/j.vlsi.2025.102380
Yingchun Lu , Changlong Cao , Yang Liu , Huaguo Liang , Liang Yao , Lixiang Ma
True random number generator is a crucial hardware system component that is widely used in the fields of cryptographic communication, key generation, statistical simulation, and secure authentication. However, the related TRNG suffers from low throughput and high resource overhead due to relying on a single entropy source. To address this issue, a TRNG circuit implementation scheme based on a MUX-XOR gate cell (MX-cell) is proposed, which uses the switching characteristics of the MUX and the XOR gate to generate metastability and jitter to develop a hybrid entropy source. It further enables the dynamic superposition of entropy sources under prescribed conditions, which improves the TRNG throughput while reducing the resource overhead. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs with automatic placement and routing, passing NIST, AIS-31, TESTU01 statistical test suites and a series of other performance tests without post-processing. The experimental results reveal that the suggested design consumes only 19 LUTs, 8 DFFs, and 4 MUXs to provide random numbers with up to 380 Mbps throughput, which demonstrates highly efficient resource utilization compared to advanced published TRNGs.
{"title":"High throughput true random number generator based on dynamically superimposed hybrid entropy sources","authors":"Yingchun Lu , Changlong Cao , Yang Liu , Huaguo Liang , Liang Yao , Lixiang Ma","doi":"10.1016/j.vlsi.2025.102380","DOIUrl":"10.1016/j.vlsi.2025.102380","url":null,"abstract":"<div><div>True random number generator is a crucial hardware system component that is widely used in the fields of cryptographic communication, key generation, statistical simulation, and secure authentication. However, the related TRNG suffers from low throughput and high resource overhead due to relying on a single entropy source. To address this issue, a TRNG circuit implementation scheme based on a MUX-XOR gate cell (MX-cell) is proposed, which uses the switching characteristics of the MUX and the XOR gate to generate metastability and jitter to develop a hybrid entropy source. It further enables the dynamic superposition of entropy sources under prescribed conditions, which improves the TRNG throughput while reducing the resource overhead. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs with automatic placement and routing, passing NIST, AIS-31, TESTU01 statistical test suites and a series of other performance tests without post-processing. The experimental results reveal that the suggested design consumes only 19 LUTs, 8 DFFs, and 4 MUXs to provide random numbers with up to 380 Mbps throughput, which demonstrates highly efficient resource utilization compared to advanced published TRNGs.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102380"},"PeriodicalIF":2.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143395412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-07DOI: 10.1016/j.vlsi.2025.102378
José David Rodríguez-Muñoz , Esteban Tlelo-Cuautle , Luis Gerardo de la Fraga
In lightweight cryptographic applications, the authentication of encrypted data is a challenge that can be solved by using high-order chaotic systems. The proposed work shows that increasing the length of bits in a Hash function, leads to diminish the possibility of a collision. Using high-order chaotic systems, can also lead to use large prime numbers by exploiting the fact that the division and modulo operations provide a better distribution in a most uniform way. In addition, because a prime number has factors including 1 and himself, then this greatly reduces the appearance of repetitive patterns in a modulo operation. In this manner, this article presents the implementation of a chaos based system for authentication of encrypted RGB images using Raspberry Pi devices. First, a two dimensional (2D) map, and 3D, and 4D chaotic systems, are implemented on Raspberry Pi devices to design pseudo-random number generators (PRNG). Second, the randomness of the sequences is evaluated by performing NIST (National Institute of Standards and Technology) tests. Third, the random sequences are used to construct a stream cipher and an authenticated Hash function based on a method called pseudo dot product. Fourth, RGB images are encrypted using the PRNGs based on 2D, 3D, and 4D chaotic systems. In the proposed work, all these processes are performed under a machine-to-machine (M2M) wireless connectivity system, which is available on the message queuing telemetry transport (MQTT) communication protocol for Internet of Things (IoT). In the experiments, three Raspberry Pi devices are configured as a publisher, a broker, and a subscriber to work on MQTT for sending and receiving encrypted RGB images, while the images are authenticated through the evaluation of Hash function tags, which are generated by using 2D, 3D, and 4D chaotic systems. The main conclusion is that the encryption/decryption and authentication processes are much better when using high-dimensional chaotic systems.
{"title":"Chaos-based authentication of encrypted images under MQTT for IoT protocol","authors":"José David Rodríguez-Muñoz , Esteban Tlelo-Cuautle , Luis Gerardo de la Fraga","doi":"10.1016/j.vlsi.2025.102378","DOIUrl":"10.1016/j.vlsi.2025.102378","url":null,"abstract":"<div><div>In lightweight cryptographic applications, the authentication of encrypted data is a challenge that can be solved by using high-order chaotic systems. The proposed work shows that increasing the length of bits in a Hash function, leads to diminish the possibility of a collision. Using high-order chaotic systems, can also lead to use large prime numbers by exploiting the fact that the division and modulo operations provide a better distribution in a most uniform way. In addition, because a prime number has factors including 1 and himself, then this greatly reduces the appearance of repetitive patterns in a modulo operation. In this manner, this article presents the implementation of a chaos based system for authentication of encrypted RGB images using Raspberry Pi devices. First, a two dimensional (2D) map, and 3D, and 4D chaotic systems, are implemented on Raspberry Pi devices to design pseudo-random number generators (PRNG). Second, the randomness of the sequences is evaluated by performing NIST (National Institute of Standards and Technology) tests. Third, the random sequences are used to construct a stream cipher and an authenticated Hash function based on a method called pseudo dot product. Fourth, RGB images are encrypted using the PRNGs based on 2D, 3D, and 4D chaotic systems. In the proposed work, all these processes are performed under a machine-to-machine (M2M) wireless connectivity system, which is available on the message queuing telemetry transport (MQTT) communication protocol for Internet of Things (IoT). In the experiments, three Raspberry Pi devices are configured as a publisher, a broker, and a subscriber to work on MQTT for sending and receiving encrypted RGB images, while the images are authenticated through the evaluation of Hash function tags, which are generated by using 2D, 3D, and 4D chaotic systems. The main conclusion is that the encryption/decryption and authentication processes are much better when using high-dimensional chaotic systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102378"},"PeriodicalIF":2.2,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-01DOI: 10.1016/j.vlsi.2025.102373
Runlian Zhang , Yu Mo , Zhaoxuan Pan , Hailong Zhang , Yongzhuang Wei , Xiaonian Wu
CutMix data augmentation can provide a large amount of augmented data for DL-SCA (deep learning side channel attacks) by generating new power traces. However, traces generated by CutMix may lose dependency with the new label, which may reduce the accuracy of the training model. In light of this, we propose an improved intra-class CutMix data augmentation method. Firstly, the original traces are classified by the label. Then, the original traces are selected by the same label constraint to generate new traces according to CutMix, which can ensure the dependency between the generated trace and its label. Furthermore, in order to maintain balance among different classified datasets, the traces are generated sequentially according to distinct labels. Finally, based on the augmented traces, the Multilayer Perceptron (MLP) and Convolutional Neural Network (CNN) models can be constructed and trained to recover the key of AES. In order to verify the effectiveness of the proposed method, we conduct experimental evaluations using the MLP and CNN models based on DPA-contest v4 dataset and ASCAD dataset. The test results show that the traces generated with the intra-class CutMix method can be very similar to the original traces, and the MLP and CNN models can be effectively trained based on the generated traces to recover the key of AES. Besides, compared with existing data augmentation methods, the proposed method can complete secret key recovery with faster convergence and fewer traces.
{"title":"Intra-class CutMix data augmentation based deep learning side channel attacks","authors":"Runlian Zhang , Yu Mo , Zhaoxuan Pan , Hailong Zhang , Yongzhuang Wei , Xiaonian Wu","doi":"10.1016/j.vlsi.2025.102373","DOIUrl":"10.1016/j.vlsi.2025.102373","url":null,"abstract":"<div><div>CutMix data augmentation can provide a large amount of augmented data for DL-SCA (deep learning side channel attacks) by generating new power traces. However, traces generated by CutMix may lose dependency with the new label, which may reduce the accuracy of the training model. In light of this, we propose an improved intra-class CutMix data augmentation method. Firstly, the original traces are classified by the label. Then, the original traces are selected by the same label constraint to generate new traces according to CutMix, which can ensure the dependency between the generated trace and its label. Furthermore, in order to maintain balance among different classified datasets, the traces are generated sequentially according to distinct labels. Finally, based on the augmented traces, the Multilayer Perceptron (MLP) and Convolutional Neural Network (CNN) models can be constructed and trained to recover the key of AES. In order to verify the effectiveness of the proposed method, we conduct experimental evaluations using the MLP and CNN models based on DPA-contest v4 dataset and ASCAD dataset. The test results show that the traces generated with the intra-class CutMix method can be very similar to the original traces, and the MLP and CNN models can be effectively trained based on the generated traces to recover the key of AES. Besides, compared with existing data augmentation methods, the proposed method can complete secret key recovery with faster convergence and fewer traces.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102373"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-01DOI: 10.1016/j.vlsi.2025.102379
Kaveri Hatti, C. Paramasivam
Physical unclonable functions (PUF) are a type of physical system that harvests data from integrated circuits fragile physical components. These systems offer a highly secure way to generate cryptographic keys for cryptographic operations and protect secure IPs from threats, manipulation, and duplication due to their un-clonability properties. Prior literature has designed various Arbiter PUFs with 2:1 MUX, but they consume a large area to generate the larger response bits. Based on our literature survey, this is the first paper to design an Arbiter PUF with 4:1 MUX, which reduces the area overhead. This paper utilizes a 4:1MUX APUF design is implemented on 10 ZYNQ-7000 SoC FPGA devices using the LUT6 primitive to overcome the challenge of designing an unbiased PUF architecture on the FPGA device. The study also presents two different methodologies to generate responses for the corresponding challenge of 4:1 MUX Arbiter PUF. The design showed a uniqueness rate of 49 % when evaluated on both methodologies. The dependability percentages for temperature fluctuations (20–70 °C) were 99 %. Finally, the performance parameter of the proposed PUF is state-of-the-art.
{"title":"Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA","authors":"Kaveri Hatti, C. Paramasivam","doi":"10.1016/j.vlsi.2025.102379","DOIUrl":"10.1016/j.vlsi.2025.102379","url":null,"abstract":"<div><div>Physical unclonable functions (PUF) are a type of physical system that harvests data from integrated circuits fragile physical components. These systems offer a highly secure way to generate cryptographic keys for cryptographic operations and protect secure IPs from threats, manipulation, and duplication due to their un-clonability properties. Prior literature has designed various Arbiter PUFs with 2:1 MUX, but they consume a large area to generate the larger response bits. Based on our literature survey, this is the first paper to design an Arbiter PUF with 4:1 MUX, which reduces the area overhead. This paper utilizes a 4:1MUX APUF design is implemented on 10 ZYNQ-7000 SoC FPGA devices using the LUT6 primitive to overcome the challenge of designing an unbiased PUF architecture on the FPGA device. The study also presents two different methodologies to generate responses for the corresponding challenge of 4:1 MUX Arbiter PUF. The design showed a uniqueness rate of 49 % when evaluated on both methodologies. The dependability percentages for temperature fluctuations (20–70 °C) were 99 %. Finally, the performance parameter of the proposed PUF is state-of-the-art.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102379"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-01DOI: 10.1016/j.vlsi.2025.102367
Garett Cunningham , Siqin Liu , Harsha Chenji , David Juedes , Avinash Karanth
As embedded systems with manycores and Network-on-Chips (NoCs) become ubiquitous, emerging hardware and software vulnerabilities have made it challenging to ensure system integrity especially when third-party intellectual property (IP) is used for rapid prototyping. Prior works have evaluated hardware monitors for ensuring correctness of the system by threat assessment and effective mitigation. However, none have evaluated models that combine both computation (processor pipeline) and communication (NoC) vulnerabilities simultaneously. In this paper, we propose a high-level policy language called d-GUARD that is used to define runtime security policies that can be compiled into hardware monitors. The advantage of this new language is the ability to dynamically change policies based on program’s runtime behavior. To translate high-level policies into low-level hardware monitors, we describe a compiler for d-GUARD that synthesizes policies into Verilog modules. Instead of simply evaluating the design of secure policies for processor pipelines, we extend to secure NoC microarchitectures, including policies for links and routers, as well as policies to prevent Denial-of-Service (DoS) attacks. To mitigate attacks against secure microarchitectures, we also propose fault-tolerant routing approaches to avoid rogue routers when the number of policy violations exceeds a certain threshold. Our secure policies for processor pipelines and NoC microarchitectures consume marginal area and power overhead when compared to baseline making it well suited for low-cost embedded systems.
{"title":"Language semantics to support secure computation and communication in embedded systems via hardware monitors","authors":"Garett Cunningham , Siqin Liu , Harsha Chenji , David Juedes , Avinash Karanth","doi":"10.1016/j.vlsi.2025.102367","DOIUrl":"10.1016/j.vlsi.2025.102367","url":null,"abstract":"<div><div>As embedded systems with manycores and Network-on-Chips (NoCs) become ubiquitous, emerging hardware and software vulnerabilities have made it challenging to ensure system integrity especially when third-party intellectual property (IP) is used for rapid prototyping. Prior works have evaluated hardware monitors for ensuring correctness of the system by threat assessment and effective mitigation. However, none have evaluated models that combine both computation (processor pipeline) and communication (NoC) vulnerabilities simultaneously. In this paper, we propose a high-level policy language called d-GUARD that is used to define runtime security policies that can be compiled into hardware monitors. The advantage of this new language is the ability to dynamically change policies based on program’s runtime behavior. To translate high-level policies into low-level hardware monitors, we describe a compiler for d-GUARD that synthesizes policies into Verilog modules. Instead of simply evaluating the design of secure policies for processor pipelines, we extend to secure NoC microarchitectures, including policies for links and routers, as well as policies to prevent Denial-of-Service (DoS) attacks. To mitigate attacks against secure microarchitectures, we also propose fault-tolerant routing approaches to avoid rogue routers when the number of policy violations exceeds a certain threshold. Our secure policies for processor pipelines and NoC microarchitectures consume marginal area and power overhead when compared to baseline making it well suited for low-cost embedded systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102367"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-01DOI: 10.1016/j.vlsi.2025.102376
Hao Wang, Ping Luo, Xiangwen Xin, Yunze Li
In this paper, a 0.1–4.2V input boost converter with 1.5 μA quiescent current consumption for microscale photovoltaic energy harvesting applications is proposed. The chip integrates a charge-pump-based three-phase self-start circuit that actives the converter with an input voltage of 0.6V. Moreover, the proposed self-start circuit reduces the capacitance area of charge pump by 40 % and the energy loss by 60 % compared to traditional two-phase self-start circuit. After completing self-start, the converter is capable of harvesting energy from an input voltage as low as 100 mV and covering a wide output power range of 5μW-460mW. The on-time of the high-side switch adapts dynamically to the input and output voltages for zero-current switching by adopting an adaptive zero current detector. The proposed chip has been fabricated using 180 nm CMOS technology and occupies an active area of 0.58 mm2. According to the measured efficiency at different load current, a peak efficiency of 93.7 % is achieved.
{"title":"A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting","authors":"Hao Wang, Ping Luo, Xiangwen Xin, Yunze Li","doi":"10.1016/j.vlsi.2025.102376","DOIUrl":"10.1016/j.vlsi.2025.102376","url":null,"abstract":"<div><div>In this paper, a 0.1–4.2V input boost converter with 1.5 μA quiescent current consumption for microscale photovoltaic energy harvesting applications is proposed. The chip integrates a charge-pump-based three-phase self-start circuit that actives the converter with an input voltage of 0.6V. Moreover, the proposed self-start circuit reduces the capacitance area of charge pump by 40 % and the energy loss by 60 % compared to traditional two-phase self-start circuit. After completing self-start, the converter is capable of harvesting energy from an input voltage as low as 100 mV and covering a wide output power range of 5μW-460mW. The on-time of the high-side switch adapts dynamically to the input and output voltages for zero-current switching by adopting an adaptive zero current detector. The proposed chip has been fabricated using 180 nm CMOS technology and occupies an active area of 0.58 mm<sup>2</sup>. According to the measured efficiency at different load current, a peak efficiency of 93.7 % is achieved.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102376"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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