Integration-The Vlsi Journal最新文献

英文中文

Optimizing value prediction for ILP processors: A design space exploration approach

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-17 DOI: 10.1016/j.vlsi.2025.102402

Ling Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu

Value prediction is a microarchitectural technique that enhances processor performance by speculatively breaking true data dependencies. It has demonstrated improved performance in both single-threaded and multi-threaded workloads, rendering it an appealing microarchitectural approach. While high-performance value predictors can achieve impressive accuracy, they may also incur significant costs in terms of area, power consumption, and complexity. Therefore, there is a demand for lightweight value prediction techniques capable of striking a favorable balance between performance and overhead. However, designing value predictors with superior performance using limited resources presents an urgent challenge, as inappropriate parameter configurations may result in cost overruns and degraded processor performance. Consequently, this work proposes a design space exploration framework for the state-of-the-art EVES value predictor, aiming to efficiently configure the design parameters of the value predictor within constrained RAM resources. Additionally, the article evaluates the performance of the explored value predictor across a wide range of workloads. The explored value predictors exhibit high efficiency across RAM sizes ranging from 2KB to 16KB while maintaining acceptable computational complexity. Furthermore, the results indicate that the explored value predictor achieves optimal efficiency under the 2KB constraint, with the highest acceleration-to-cost ratio reaching 8.74% per KB, approximately three times greater than that of the current state-of-the-art value predictor.

{"title":"Optimizing value prediction for ILP processors: A design space exploration approach","authors":"Ling Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu","doi":"10.1016/j.vlsi.2025.102402","DOIUrl":"10.1016/j.vlsi.2025.102402","url":null,"abstract":"<div><div>Value prediction is a microarchitectural technique that enhances processor performance by speculatively breaking true data dependencies. It has demonstrated improved performance in both single-threaded and multi-threaded workloads, rendering it an appealing microarchitectural approach. While high-performance value predictors can achieve impressive accuracy, they may also incur significant costs in terms of area, power consumption, and complexity. Therefore, there is a demand for lightweight value prediction techniques capable of striking a favorable balance between performance and overhead. However, designing value predictors with superior performance using limited resources presents an urgent challenge, as inappropriate parameter configurations may result in cost overruns and degraded processor performance. Consequently, this work proposes a design space exploration framework for the state-of-the-art EVES value predictor, aiming to efficiently configure the design parameters of the value predictor within constrained RAM resources. Additionally, the article evaluates the performance of the explored value predictor across a wide range of workloads. The explored value predictors exhibit high efficiency across RAM sizes ranging from 2KB to 16KB while maintaining acceptable computational complexity. Furthermore, the results indicate that the explored value predictor achieves optimal efficiency under the 2KB constraint, with the highest acceleration-to-cost ratio reaching 8.74% per KB, approximately three times greater than that of the current state-of-the-art value predictor.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102402"},"PeriodicalIF":2.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-15 DOI: 10.1016/j.vlsi.2025.102411

Jincan Zhang, Haiyi Cai, Shaowei Wang, Min Liu

In this paper, a novel intrinsic-parameters-correlation-enhancement method combining Principal Component Analysis (PCA) algorithm and Particle Swarm Optimization (PSO) algorithm for extracting intrinsic parameters of GaN High Electron Mobility Transistors (HEMT) is proposed. The traditional intrinsic parameter extraction methods are time-consuming and have low accuracy for modeling S-parameter. In order to improve the model accuracy, the PSO algorithm can be used to optimize the intrinsic parameters. However, the PSO algorithm does not consider the correlation of the intrinsic parameters, which leads to a limited improvement in model accuracy. To further improve the model accuracy, in this paper, the PCA algorithm is used to process the real and imaginary parts of the intrinsic model Y-parameters, which can enhance the correlation between intrinsic parameters. Then, the new intrinsic model Y-parameters and the PSO algorithm are used to extract the intrinsic parameters. To validate the effective of the proposed technology, it is applied to extract GaN HEMT small-signal model parameters in the frequency range of 0.5–20.5 GHz, and the experimental results show that the S-parameter modeling accuracy is effectively improved.

{"title":"A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters","authors":"Jincan Zhang, Haiyi Cai, Shaowei Wang, Min Liu","doi":"10.1016/j.vlsi.2025.102411","DOIUrl":"10.1016/j.vlsi.2025.102411","url":null,"abstract":"<div><div>In this paper, a novel intrinsic-parameters-correlation-enhancement method combining Principal Component Analysis (PCA) algorithm and Particle Swarm Optimization (PSO) algorithm for extracting intrinsic parameters of GaN High Electron Mobility Transistors (HEMT) is proposed. The traditional intrinsic parameter extraction methods are time-consuming and have low accuracy for modeling <em>S</em>-parameter. In order to improve the model accuracy, the PSO algorithm can be used to optimize the intrinsic parameters. However, the PSO algorithm does not consider the correlation of the intrinsic parameters, which leads to a limited improvement in model accuracy. To further improve the model accuracy, in this paper, the PCA algorithm is used to process the real and imaginary parts of the intrinsic model <em>Y</em>-parameters, which can enhance the correlation between intrinsic parameters. Then, the new intrinsic model <em>Y</em>-parameters and the PSO algorithm are used to extract the intrinsic parameters. To validate the effective of the proposed technology, it is applied to extract GaN HEMT small-signal model parameters in the frequency range of 0.5–20.5 GHz, and the experimental results show that the <em>S</em>-parameter modeling accuracy is effectively improved.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102411"},"PeriodicalIF":2.2,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low power SAR ADC with fine–tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-14 DOI: 10.1016/j.vlsi.2025.102407

Naveen Kandpal, Anil Singh, Alpana Agarwal

This work proposes an adaptive sampling SAR Analog-to-Digital converter (ADC) with a novel fine-tuned time-based sampling technique to dynamically adjust the sample rate for normal and abnormal ECG signals based on the characteristics of the incoming ECG signal. By integrating machine learning, the ADC adapts to varying signal conditions, ensuring accurate capture of essential data while maintaining energy efficiency, thereby enhancing the effectiveness of portable and wearable health monitoring devices. Unlike conventional methods, the Analog front end uses a time-based technique that effectively identifies and digitizes all critical information present in ECG signals. Additionally, the ADC incorporates a variable resolution scheme, enhancing power efficiency and reducing data bandwidth. The ADC adaptively allocates more bits to the most significant portions of the ECG waveform while reducing the resolution for less critical segments by employing a time-based approach. This enables efficient data representation and reduces overall data transfer requirements, making this architecture more power-efficient. Implemented in 180 nm CMOS technology, the proposed ADC consumes only 498.6 μW with a 1.8 V supply and achieves ENOB of 5.21 bits, SNDR of 31.76 dB, and SFDR of 44.31 dB. The sampling frequency of the proposed architecture changes from 64 Hz to 512 Hz, which is suitable for portable ECG monitoring applications. The FoM of the proposed work ranges from 100 to 262 fj/conversion-step for 64–512 Hz sampling rate, respectively.

{"title":"A low power SAR ADC with fine–tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS","authors":"Naveen Kandpal, Anil Singh, Alpana Agarwal","doi":"10.1016/j.vlsi.2025.102407","DOIUrl":"10.1016/j.vlsi.2025.102407","url":null,"abstract":"<div><div>This work proposes an adaptive sampling SAR Analog-to-Digital converter (ADC) with a novel fine-tuned time-based sampling technique to dynamically adjust the sample rate for normal and abnormal ECG signals based on the characteristics of the incoming ECG signal. By integrating machine learning, the ADC adapts to varying signal conditions, ensuring accurate capture of essential data while maintaining energy efficiency, thereby enhancing the effectiveness of portable and wearable health monitoring devices. Unlike conventional methods, the Analog front end uses a time-based technique that effectively identifies and digitizes all critical information present in ECG signals. Additionally, the ADC incorporates a variable resolution scheme, enhancing power efficiency and reducing data bandwidth. The ADC adaptively allocates more bits to the most significant portions of the ECG waveform while reducing the resolution for less critical segments by employing a time-based approach. This enables efficient data representation and reduces overall data transfer requirements, making this architecture more power-efficient. Implemented in 180 nm CMOS technology, the proposed ADC consumes only 498.6 μW with a 1.8 V supply and achieves ENOB of 5.21 bits, SNDR of 31.76 dB, and SFDR of 44.31 dB. The sampling frequency of the proposed architecture changes from 64 Hz to 512 Hz, which is suitable for portable ECG monitoring applications. The FoM of the proposed work ranges from 100 to 262 fj/conversion-step for 64–512 Hz sampling rate, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102407"},"PeriodicalIF":2.2,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143636643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-08 DOI: 10.1016/j.vlsi.2025.102388

Youcef Alloun , Abdenour Kifouche , Mohamed Salah Azzaz , Mahdi Madani , El-Bay Bourennane , Said Sadoudi

A secure random number generator (RNG) is crucial for cryptography and data protection applications. Many existing approaches employ classical chaotic systems, which have been demonstrated as vulnerable to some attacks. Therefore, this research proposes the design on FPGA of a new pseudo-RNG based on an artificial neural network (ANN) and chaotic systems. Initially, a multi-layer perceptron (MLP) with a hardware friendly activation function (AF) is trained to mimic the behavior of the unified chaotic system (UCS). To mitigate chaos degradation and the difference between the training and the inference, the scheduled sampling technique is adapted and applied to the MLP network. Once the model is well-tuned, its chaotic nature is validated by calculating the Lyapunov exponents and determining the fractal dimension. The pre-trained model based on which an MLP-based Chaotic Pseudo-RNG (MLP-CPRNG) is then implemented on FPGA using VHDL language and Xilinx Vivado design suite. To improve the generator’s output capabilities, a technique named the

d

-lagged differencing (

d

-LD) is implemented as a part of the MLP-CPRNG. The implemented MLP-CPRNG outperforms the existing works in terms of resource utilization, which makes it suitable for resource-constrained environment. It also offers extended key space and has successfully passed performance tests such as NIST statistical tests, entropy measurement, and correlation analysis. These results highlight the robustness of MLP-CPRNG against brute-force, algebraic and statistical attacks, thus its suitability for embedded cryptographic applications.

{"title":"Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems","authors":"Youcef Alloun , Abdenour Kifouche , Mohamed Salah Azzaz , Mahdi Madani , El-Bay Bourennane , Said Sadoudi","doi":"10.1016/j.vlsi.2025.102388","DOIUrl":"10.1016/j.vlsi.2025.102388","url":null,"abstract":"<div><div>A secure random number generator (RNG) is crucial for cryptography and data protection applications. Many existing approaches employ classical chaotic systems, which have been demonstrated as vulnerable to some attacks. Therefore, this research proposes the design on FPGA of a new pseudo-RNG based on an artificial neural network (ANN) and chaotic systems. Initially, a multi-layer perceptron (MLP) with a hardware friendly activation function (AF) is trained to mimic the behavior of the unified chaotic system (UCS). To mitigate chaos degradation and the difference between the training and the inference, the scheduled sampling technique is adapted and applied to the MLP network. Once the model is well-tuned, its chaotic nature is validated by calculating the Lyapunov exponents and determining the fractal dimension. The pre-trained model based on which an MLP-based Chaotic Pseudo-RNG (MLP-CPRNG) is then implemented on FPGA using VHDL language and Xilinx Vivado design suite. To improve the generator’s output capabilities, a technique named the <span><math><mi>d</mi></math></span>-lagged differencing (<span><math><mi>d</mi></math></span>-LD) is implemented as a part of the MLP-CPRNG. The implemented MLP-CPRNG outperforms the existing works in terms of resource utilization, which makes it suitable for resource-constrained environment. It also offers extended key space and has successfully passed performance tests such as NIST statistical tests, entropy measurement, and correlation analysis. These results highlight the robustness of MLP-CPRNG against brute-force, algebraic and statistical attacks, thus its suitability for embedded cryptographic applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102388"},"PeriodicalIF":2.2,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143592130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-07 DOI: 10.1016/j.vlsi.2025.102390

Lintao Li , Xiaoxia Yao , Yimin Li , Ran Zhu , Jiayi Lv , Hua Li

This paper presents a resource-efficient, ultra-high throughput low density parity check (LDPC) decoder that is suitable for tens of gigabit bits per second satellite communications. To address routing congestion and critical path delay, which are typically caused by the high degree of parallelism in high throughput decoder designs, this work introduces an efficient computation circuit for identifying the two minimum values in the check node update process. Furthermore, a non-uniform quantization method based on mutual information maximization is proposed for log-likelihood ratio (LLR) representation, enabling a more favorable trade-off between decoding performance and implementation complexity. Additionally, the decoder utilizes a pipelined multi-frame parallel scheduling scheme, which significantly boosts throughput with only a slight increase in storage requirements. Finally, the proposed design is implemented and tested on a Xilinx UltraScale+ XCVU13P FPGA. The results show that the decoder achieves a throughput of 76.5Gbps at 8 iterations and 200MHz. This implementation outperforms existing designs, highlighting the innovative and superior nature of our approach.

{"title":"Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard","authors":"Lintao Li , Xiaoxia Yao , Yimin Li , Ran Zhu , Jiayi Lv , Hua Li","doi":"10.1016/j.vlsi.2025.102390","DOIUrl":"10.1016/j.vlsi.2025.102390","url":null,"abstract":"<div><div>This paper presents a resource-efficient, ultra-high throughput low density parity check (LDPC) decoder that is suitable for tens of gigabit bits per second satellite communications. To address routing congestion and critical path delay, which are typically caused by the high degree of parallelism in high throughput decoder designs, this work introduces an efficient computation circuit for identifying the two minimum values in the check node update process. Furthermore, a non-uniform quantization method based on mutual information maximization is proposed for log-likelihood ratio (LLR) representation, enabling a more favorable trade-off between decoding performance and implementation complexity. Additionally, the decoder utilizes a pipelined multi-frame parallel scheduling scheme, which significantly boosts throughput with only a slight increase in storage requirements. Finally, the proposed design is implemented and tested on a Xilinx UltraScale+ XCVU13P FPGA. The results show that the decoder achieves a throughput of 76.5Gbps at 8 iterations and 200MHz. This implementation outperforms existing designs, highlighting the innovative and superior nature of our approach.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102390"},"PeriodicalIF":2.2,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and practical implementation of a novel hyperchaotic system generator based on Apéry's constant

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102399

Omer Kocak , Uğur Erkan , Ismail Babaoglu

Modern chaotic systems necessitate high levels of randomness and complexity, which can be achieved through adaptable seed functions. This paper proposes a new 2D Apéry chaotic system generator (2D-ACG) based on Apéry numbers to fulfill this need. The 2D-ACG generates various chaotic systems using classical seed functions. The effectiveness and the capabilities of 2D-ACG are demonstrated on three well-known example chaotic maps using pairs of seed functions such as Cos-Cos, Sin-Sin and Cos-Sin. The reliability of chaos metrics, such as the Lyapunov exponent (LE), sample entropy (SE), correlation dimension (CD), Kolmogorov entropy (KE), C0 test, and sensitivity, confirms the chaotic performance of these maps. This is further supported by a comparison with reported 2D chaotic systems. Furthermore, one of the maps derived from 2D-ACG has been implemented into an image encryption algorithm and has successfully passed the cryptanalysis tests. Additionally, the hardware implementation of 2D-ACG has been tested on a field programmable gate array (FPGA), thereby confirming its efficacy. The superior results obtained indicate that the proposed 2D-ACG, with its enhanced diversity and complex structure derived from the Apéry's constant, exhibits higher-performance chaotic characteristics.

{"title":"Design and practical implementation of a novel hyperchaotic system generator based on Apéry's constant","authors":"Omer Kocak , Uğur Erkan , Ismail Babaoglu","doi":"10.1016/j.vlsi.2025.102399","DOIUrl":"10.1016/j.vlsi.2025.102399","url":null,"abstract":"<div><div>Modern chaotic systems necessitate high levels of randomness and complexity, which can be achieved through adaptable seed functions. This paper proposes a new 2D Apéry chaotic system generator (2D-ACG) based on Apéry numbers to fulfill this need. The 2D-ACG generates various chaotic systems using classical seed functions. The effectiveness and the capabilities of 2D-ACG are demonstrated on three well-known example chaotic maps using pairs of seed functions such as Cos-Cos, Sin-Sin and Cos-Sin. The reliability of chaos metrics, such as the Lyapunov exponent (LE), sample entropy (SE), correlation dimension (CD), Kolmogorov entropy (KE), C0 test, and sensitivity, confirms the chaotic performance of these maps. This is further supported by a comparison with reported 2D chaotic systems. Furthermore, one of the maps derived from 2D-ACG has been implemented into an image encryption algorithm and has successfully passed the cryptanalysis tests. Additionally, the hardware implementation of 2D-ACG has been tested on a field programmable gate array (FPGA), thereby confirming its efficacy. The superior results obtained indicate that the proposed 2D-ACG, with its enhanced diversity and complex structure derived from the Apéry's constant, exhibits higher-performance chaotic characteristics.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102399"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143609484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102400

Lokenath Kundu , Subhanil Maity , Sourav Nath , Gaurav Singh Baghel , Krishna Lal Baishnab

This work presents novel single-ended (Design I and Design II) and double-ended (Design III and Design IV) architectures of 2/3 frequency dividers (FDs) that improve power delay product (PDP) and power consumption. This novel work proposes four kinds of 2/3 dual modulus FDs that are compatible with ZigBee and Bluetooth communication standards. The proposed designs are also tunable for different communication bands and are based on current mode logic (CML) in the 2.4–2.8 GHz PLL application range. The subblocks of 2/3 dual modulus FDs use CML-based latches, XOR gates, and delay cells to achieve the desired functionality. The g_m over I_d (g_m/I_d) methodology is explored for the optimum design of latches, enabling efficient circuit sizing and enhanced performance. This lowers the total power consumption to 0.6 mW with a power delay product (PDP) of 1 fJ. These proposed designs are post-layout simulated using a TSMC 65 nm CMOS process technology node. These designs are compared with the recent post-layout performances of state-of-the-art works with 30.6 dB of figure of merits (FoM). This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage, and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).

{"title":"Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application","authors":"Lokenath Kundu , Subhanil Maity , Sourav Nath , Gaurav Singh Baghel , Krishna Lal Baishnab","doi":"10.1016/j.vlsi.2025.102400","DOIUrl":"10.1016/j.vlsi.2025.102400","url":null,"abstract":"<div><div>This work presents novel single-ended (Design I and Design II) and double-ended (Design III and Design IV) architectures of 2/3 frequency dividers (FDs) that improve power delay product (PDP) and power consumption. This novel work proposes four kinds of 2/3 dual modulus FDs that are compatible with ZigBee and Bluetooth communication standards. The proposed designs are also tunable for different communication bands and are based on current mode logic (CML) in the 2.4–2.8 GHz PLL application range. The subblocks of 2/3 dual modulus FDs use CML-based latches, XOR gates, and delay cells to achieve the desired functionality. The g<sub>m</sub> over I<sub>d</sub> (g<sub>m</sub>/I<sub>d</sub>) methodology is explored for the optimum design of latches, enabling efficient circuit sizing and enhanced performance. This lowers the total power consumption to 0.6 mW with a power delay product (PDP) of 1 fJ. These proposed designs are post-layout simulated using a TSMC 65 nm CMOS process technology node. These designs are compared with the recent post-layout performances of state-of-the-art works with 30.6 dB of figure of merits (FoM). This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage, and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102400"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143579833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Rich dynamics and analog implementation of a Hopfield neural network in integer and fractional order domains

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102389

Diego S. de la Vega , Jesus M. Munoz-Pacheco , Olga G. Félix-Beltrán , Christos Volos

Several synaptic weight matrices have been proposed for Hopfield neural network (HNN) models, where chaotic dynamics may arise. Contrary to those works, this manuscript aims to present a synaptic weight matrix where every entry can be set as an integer, harvesting an elegant chaotic HNN from a chaos theory point of view. Analytical and numerical analyses such as equilibrium points, bifurcation diagrams, Lyapunov exponents, and basins of attraction demonstrate that the proposed HNN exhibits complex behaviors across a wide range of parameter values. Also, we extend the study of the HNN into the fractional order domain. Moreover, the design and implementation details of the proposed neural network using field programmable analog arrays (FPAAs) are thoroughly discussed. This includes the various components and their configurations, highlighting how they contribute to the overall functionality of the neural network. As a result, we found a strong correlation between numerical simulations and SPICE circuit simulations.

引用次数: 0

Low test cost adaptive testing method for high yield IC products

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-03-04 DOI: 10.1016/j.vlsi.2025.102401

Yuqi Pan, Huaguo Liang, Junming Li, Zhengfeng Huang, Maoxiang Yi, Yingchun Lu

The ever-increasing complexity of integrated circuits inevitably leads to high chip test cost. Machine learning techniques can predict chip quality with a small number of test items, but require a similar number of passed and failed chips in the training data. Training a model with high yield chip data results in a large number of test escapes. In order to reduce the test cost and maintain the recognition rate of failed chips, an adaptive testing method based on ensemble learning is proposed. The degree of imbalance in the test data is alleviated by undersampling, and then the test items are filtered based on the model classification effects. Finally, to prevent imbalanced data from disturbing the ensemble learning algorithm, boundary adjustment is used to reduce test escapes. Experimental results using fabricated chips test data show that the proposed method reduces more than 34 % of test items in the face of high yield chips, and the accuracy of the classification of failed chips reaches more than 99 %.

引用次数: 0

The effect of ECG data variability on side-channel attack success rate in wearable devices

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-02-28 DOI: 10.1016/j.vlsi.2025.102385

Pablo Perez-Tirador , Ruzica Jevtic , Carmen Cabezaolias , Teresa Romero , Abraham Otero , Gabriel Caffarena

As the connectivity and number of health monitoring devices has increased dramatically in recent years, various security issues have become a serious threat to the integrity of patient data. Side-channel attacks are particularly dangerous for these devices because they do not rely on the mathematical complexity of the cryptographic algorithm, but instead exploit physical information leakage. In this work, we analyze electromagnetic and power side-channel attacks on portable electrocardiogram (ECG) monitoring devices. Unlike other work that uses random data, we analyze attacks based on real ECG data and show that the data distribution significantly affects the success rate of the attacks. We build a wearable ECG garment that records a single-lead ECG and sends it to a low-power microcontroller for encryption using AES. The results show that the first-round attack success rate is strongly influenced by the number of bits used to encrypt each ECG sample and the intensity level of the patient’s physical activity. More intense activity produces more artifacts in the ECG that increase the overall signal variability. An increase in variability generally results in an 86% reduction in the number of power samples required for an attack. The final attack also shows a dependence on input variability, but to a lesser extent. Input data with higher variability reduces the number of traces required for this attack by up to 50%, and the attack only becomes unsuccessful in the presence of extremely high levels of noise during the ECG recording. Based on these results, mitigation measures that exploit a change in signal variability are proposed.

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