Integration-The Vlsi Journal最新文献

A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB-OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC $0.18\mu m$ process. The simulated results demonstrate that the proposed LPFBR-OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB-OTA under the condition that LCMFB resistors are increased by a factor of 10.

An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.

As chip designs grow in complexity, the optical proximity correction (OPC) process becomes increasingly time-consuming. As a result, pattern search technology is becoming a foundation stone of many tasks for manufacturing, such as lithography simulation, hotspot detection, mask optimization, and so on. The most difficult challenge of pattern search is to locate clips by specific patterns within the layout accurately and efficiently. In this paper, we present a generalized pattern search method capable in diverse scenarios, including patterns with hollow shapes, shifting edges, and multi-layer situations. Experimental results show that our method outperforms commercial tools in pattern locating accuracy and handling search problems involving complex patterns which is not directly support by commercial tools yet.

In this paper, the circuit simulation is achieved by the established Hindmarsh-Rose (HR) neuron model and the system is applied in projection synchronization. The chaotic behaviors of the neural network model are analyzed using bifurcation diagrams, Lyapunov exponents spectra, phase diagrams and time series diagrams. The dynamics analysis of the neuron model shows a variety of firing behaviors and extreme multistability behavior. The model is then simulated through circuit multisim to demonstrate the possibility in a physical sense. Finally, synchronization is induced to the memristive neural system through projection control, and the experimental results show that the model embodies a good synchronization effect in the process of projection synchronization, which helps to improve the security of signal transmission and the confidentiality of the system, and lays the foundation for the secure communication afterwards.

-This article designs and develops a wide-input voltage, high-efficiency, small-size, and peak current-mode control step-down DC-DC converter. The Cadence Spectre simulation tool is used for system simulation to verify the performance of the chip. The overall research content of the article includes the function of the output under heavy load, light load and the stability of the output under transient load changes. The specific content of the research is buck synchronous step-down DC-DC converter chip with pulse modulated. It is provided with an input-voltage range of 6 V–80 V and maximum output-voltage range 72 V. The chip possesses wide operating temperature range of −20 °C to 130 °C. The 92 % high-efficiency can be achieved by using a PWM/PFM hybrid modulation method. When achieving transient load jump, the output voltage change shall not exceed 150 mV. The maximum load current of the chip is 1 A. Furthermore, the chip is packaged and samples can be obtained, and the output light load/heavy load, and other functions are tested through the circuit board. In addition, the chip achieved tape out by using 0.18 μm CMOS process with size of 2027 μm $\times$ 2020 μm. The converter features current mode control to simplify external compensation and optimize transient response through a wide range of inductors and output capacitors. It can be adopted user-programmable soft-start time to prevent inrush current during startup. It also includes thermal shutdown protection to provide safe and smooth operation in operating conditions.

The prevalent utilization of symmetric block ciphers in contemporary information security systems reinforces the need for immediate action to increase their effectiveness. This task is considered crucial in the synthesis of high-quality cryptographic primitives, particularly S-boxes. In accordance with this requirement, the current article demonstrates a strategy for generating an 8 × 8 S-box drawing over an LA-ring of order 1024, which is considered a substantial class of non-associative rings. For the purpose of investigating LA-ring and their practical uses, it is essential to have illustrative examples. However, obtaining such examples using current methods is tedious and yields limited results. Therefore, this research explores an intriguing opportunity for an extensive exploration of LA-ring, far exceeding the limitations previously established and offering a valuable analytical approach for creating examples of higher-order LA-ring by drawing upon lower orders. The manuscript also performs a variety of standard evaluation tests based on five core indicators, which highlight their potential as parallels to the existing frameworks. By using the crafted S-box, an image encryption approach is launched that aims to enhance security measures. It is therefore seen that the recommended S-box has shown a high potential for causing confusion during the substitution phase, and a 3D chaotic map is implemented for the pixel permutation in order to create diffusion into the colour image. Certainly, the discovery is leading to a foundational framework among academics and is expected to serve as the basis for numerous implementations in the future.

The article examines methods for integrating 3D-stacked DRAM with AI logic chips, in order to overcome the memory bandwidth challenges faced in the AI inference of transformer models. The findings indicate that this approach can yield a 9x to 3x reduction in power consumption while maintaining similar performance levels, or alternatively, an 8x improvement in performance with comparable power consumption.

—Millimeter-wave and terahertz interconnects implemented in advanced complementary metal oxide semiconductor (CMOS) technologies have emerged as promising solutions to fix the issues encountered by baseband interconnects and optical interconnects across specific communication ranges. Over the last decade, significant attempts to advance millimeter-wave and terahertz electronics and platforms have been made. Notably, there have been ground-breaking advancements in active components, including modulation techniques, low-noise receivers, efficient and high-output-power signal generators, and high-frequency clock synthesizers. Nevertheless, since energy efficiency is of paramount importance for interconnect applications, it is necessary to prioritize efficiency enhancements over improvements in signal power, signal integrity and noise related performance. Strategies to improve system output power and phase noise as well as strategies to reduce channel loss and channel electromagnetic crosstalk should leverage alternative approaches, such as architectural optimizations and array configurations, rather than prioritizing energy efficiency. As such, the progression of passive channel technology is equally vital. While reducing channel insertion loss is essential for extending communication reach, channel dispersion and crosstalk limitations at the interface level present critical challenges to achieving optimal bandwidth over distances of up to a few meters. This underscores the need for a balanced focus on both active and passive component innovations to fully harness the potential of millimeter-wave and terahertz interconnects in overcoming the limitations of current CMOS technologies.

Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer. On industrial benchmarks, our algorithm can also achieve a 10.6% improvement in routing wirelength, 27.3% in WNS, and 34.4% in TNS.

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than $70$° phase margin and more than $10\mathrm{dB}$ gain margin with a load capacitor range of 0 to $500\mathrm{pF}$ and consumes less quiescent current. The proposed OTA uses a smaller SMC of $2\mathrm{pF}$ to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC $90\mathrm{nm}$ CMOS technology with BSIM4 MOSFETs.