IBIS Model Simulation Accuracy Improvement by Including Power-Supply-Induced Jitter Effect

Abstract

The power-aware input/output buffer information specification (IBIS) model does not correctly account for the delay change caused by supply-voltage noise. This article presents a new modification algorithm that improves the accuracy of the IBIS model by including the power-supply-induced jitter (PSIJ) sensitivity effect; more specifically, the dc-jitter-sensitivity effect. The procedure of extracting the key parameters and modifying the switching coefficients is presented and applied in a real design. The performance of the modified IBIS model is validated using two designs, and the simulation accuracy is improved significantly compared with that of the traditional IBIS model. The improved IBIS model is applicable to situations when there is dc or ac noise on the power rail. The predriver propagation delay can also be characterized in the simulation by including the predriver PSIJ effect. The algorithm is efficient while straightforward and easily implemented by introducing just one parameter to the IBIS model.