Pub Date : 2026-01-09DOI: 10.1109/TSIPI.2026.3652338
{"title":"2025 Index IEEE Transactions on Signal and Power Integrity","authors":"","doi":"10.1109/TSIPI.2026.3652338","DOIUrl":"https://doi.org/10.1109/TSIPI.2026.3652338","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2026-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11345459","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-06DOI: 10.1109/TSIPI.2025.3650011
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2025.3650011","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3650011","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11329428","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1109/TSIPI.2025.3645170
Hung Khac Le;Jisoo Hwang;Jeong-Taek Kong;SoYoung Kim
In this work, we propose a signal integrity and power efficiency optimization framework for high-speed input/output equalizer systems using deep reinforcement learning based on a deep double Q-network. Although equalizer techniques have long existed, few studies have systematically optimized the feed-forward equalizer, decision feedback equalizer, and continuous-time linear equalizer together, including the high-speed channel properties. This framework determines the parameters of the equalizer architecture to optimize performance metrics such as eye height, eye width, and power consumption. It offers three key advantages: a framework with a scalable deep neural network to efficiently model complex design challenges; a future-state technique that mitigates design-space expansion with a minimum number of output neurons; and simultaneous evaluation of power efficiency, unachievable with conventional methods. As a proof of concept, we present the optimization of equalizer architecture using the proposed approach across different high-speed channels, including a backplane and an interference-tolerant channel. Experimental results demonstrate that our approach improves signal and power performance significantly compared to those from conventional methods (e.g., minimum-mean squared error and least-mean squared) and converges much faster than genetic, particle swarm, and Bayesian optimization algorithms.
{"title":"High-Speed I/O Equalizer Optimization Based on Deep Reinforcement Learning","authors":"Hung Khac Le;Jisoo Hwang;Jeong-Taek Kong;SoYoung Kim","doi":"10.1109/TSIPI.2025.3645170","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3645170","url":null,"abstract":"In this work, we propose a signal integrity and power efficiency optimization framework for high-speed input/output equalizer systems using deep reinforcement learning based on a deep double Q-network. Although equalizer techniques have long existed, few studies have systematically optimized the feed-forward equalizer, decision feedback equalizer, and continuous-time linear equalizer together, including the high-speed channel properties. This framework determines the parameters of the equalizer architecture to optimize performance metrics such as eye height, eye width, and power consumption. It offers three key advantages: a framework with a scalable deep neural network to efficiently model complex design challenges; a future-state technique that mitigates design-space expansion with a minimum number of output neurons; and simultaneous evaluation of power efficiency, unachievable with conventional methods. As a proof of concept, we present the optimization of equalizer architecture using the proposed approach across different high-speed channels, including a backplane and an interference-tolerant channel. Experimental results demonstrate that our approach improves signal and power performance significantly compared to those from conventional methods (e.g., minimum-mean squared error and least-mean squared) and converges much faster than genetic, particle swarm, and Bayesian optimization algorithms.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"5 ","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145877108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article proposes a high-speed channel transformer (HSCT) network module to model the S-parameter of traces. To deal with length variation, RLGC matrices are modeled using transformer networks and converted by an RLGC-to-S layer. For validation, the accuracy of predicted RLGC and S-parameters is compared with conventional simulators. As a result, error rates of estimated magnitude and phase achieve 0.76% and 3.62%, respectively. The pretrained HSCT module is verified to be scalable in terms of the number of frequency points, without redefining weights and additional training. In addition, a precise analysis of the RLGC data distributions depending on preprocessing techniques is performed, hence, to ensure the reproducibility of the proposed method.
本文提出了一种高速通道变压器（HSCT）网络模块来模拟走线的s参数。为了处理长度变化，RLGC矩阵使用变压器网络建模，并通过RLGC- To - s层进行转换。为了验证，将预测的RLGC和s参数与常规模拟器的精度进行了比较。结果表明，估计幅度和相位的错误率分别达到0.76%和3.62%。通过验证预训练的HSCT模块在频率点数量上是可扩展的，无需重新定义权重和额外的训练。此外，根据预处理技术对RLGC数据分布进行了精确分析，从而确保了所提出方法的可重复性。
{"title":"High-Speed Channel Modeling Using Transformer Network","authors":"Hyunwook Park;Davit Kharshiladze;Natalia Bondarenko;Hanqin Ye;Brice Achkir;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3636438","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3636438","url":null,"abstract":"This article proposes a high-speed channel transformer (HSCT) network module to model the S-parameter of traces. To deal with length variation, RLGC matrices are modeled using transformer networks and converted by an RLGC-to-S layer. For validation, the accuracy of predicted RLGC and S-parameters is compared with conventional simulators. As a result, error rates of estimated magnitude and phase achieve 0.76% and 3.62%, respectively. The pretrained HSCT module is verified to be scalable in terms of the number of frequency points, without redefining weights and additional training. In addition, a precise analysis of the RLGC data distributions depending on preprocessing techniques is performed, hence, to ensure the reproducibility of the proposed method.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"206-217"},"PeriodicalIF":0.0,"publicationDate":"2025-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/TSIPI.2025.3621163
Fatemeh Zahedi;Esfandiar Mehrshahi;Amir Jabbari
The accurate and comprehensive modeling of interconnects system is crucial due to its effects on speed, signal integrity, and performance of the entire circuit. The novel idea of this article is to apply an efficient method to analyze crosstalk and delay of the lossy coupled interconnects system in generalized identical and nonidentical forms. For this purpose, a simple model containing capacitive and inductive coupling features is proposed under arbitrary excitation sources. More specifically, it gives comprehensive and accurate closed-form expressions according to transmission line theory to take both crosstalk and delay into account. The proposed coupling noise model is used to deal with the impacts of functional and dynamic crosstalk. Moreover, the voltage and current waveforms are efficiently calculated. The resulting crosstalk waveforms are in decent agreement with those obtained using Advanced Design System simulator. The presented technique could be extended to N coupled lines, opening new avenues to analysis of integrated circuit interconnections.
{"title":"On the Modeling and Analysis of Crosstalk Noise in Nonidentical Lossy Interconnects","authors":"Fatemeh Zahedi;Esfandiar Mehrshahi;Amir Jabbari","doi":"10.1109/TSIPI.2025.3621163","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3621163","url":null,"abstract":"The accurate and comprehensive modeling of interconnects system is crucial due to its effects on speed, signal integrity, and performance of the entire circuit. The novel idea of this article is to apply an efficient method to analyze crosstalk and delay of the lossy coupled interconnects system in generalized identical and nonidentical forms. For this purpose, a simple model containing capacitive and inductive coupling features is proposed under arbitrary excitation sources. More specifically, it gives comprehensive and accurate closed-form expressions according to transmission line theory to take both crosstalk and delay into account. The proposed coupling noise model is used to deal with the impacts of functional and dynamic crosstalk. Moreover, the voltage and current waveforms are efficiently calculated. The resulting crosstalk waveforms are in decent agreement with those obtained using Advanced Design System simulator. The presented technique could be extended to <italic>N</i> coupled lines, opening new avenues to analysis of integrated circuit interconnections.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"197-205"},"PeriodicalIF":0.0,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel balanced dispersive delay circuit (DDC) with common-mode (CM) suppression and bandpass filtering characteristics is proposed for signal integrity, analog signal processing, and group delay equalization. The utilization of parallel coupled lines not only achieves a bandpass filtering response for differential-mode signals but also suppresses the transmission of common-mode noise as well as port matching characteristics. The in-band large linear group delay shape is generated by configuring phase-asymmetric transmission paths at both ends of the stub-loaded microstrip lines. The introduction of lumped resistors can be used to adjust the linearity of the in-band group delay. To further validate the workability of the design, a microstrip prototype of the balanced filtering DDC with a simple circuit structure is fabricated and measured. Compared to the reported DDCs, the proposed one not only has in-band linear group delay and bandpass filtering responses but also extends the DDC to the balanced topology to realize an excellent CM suppression characteristic for the first time.
{"title":"Balanced Dispersive Delay Circuit With Common-Mode Suppression and Filtering Characteristics","authors":"Shipeng Zhao;Zhongbao Wang;Dehao Zhao;Hongmei Liu;Shaojun Fang","doi":"10.1109/TSIPI.2025.3621185","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3621185","url":null,"abstract":"A novel balanced dispersive delay circuit (DDC) with common-mode (CM) suppression and bandpass filtering characteristics is proposed for signal integrity, analog signal processing, and group delay equalization. The utilization of parallel coupled lines not only achieves a bandpass filtering response for differential-mode signals but also suppresses the transmission of common-mode noise as well as port matching characteristics. The in-band large linear group delay shape is generated by configuring phase-asymmetric transmission paths at both ends of the stub-loaded microstrip lines. The introduction of lumped resistors can be used to adjust the linearity of the in-band group delay. To further validate the workability of the design, a microstrip prototype of the balanced filtering DDC with a simple circuit structure is fabricated and measured. Compared to the reported DDCs, the proposed one not only has in-band linear group delay and bandpass filtering responses but also extends the DDC to the balanced topology to realize an excellent CM suppression characteristic for the first time.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"191-196"},"PeriodicalIF":0.0,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/TSIPI.2025.3608692
Junyong Park;Yuandong Guo;Bo Pu;DongHyun Kim;Jun Fan
De-embedding techniques have been introduced to evaluate the real electrical performances of a device under test (DUT), e.g., the traditional thru-reflect-line and short-open-load-thru standards, where the transfer matrix (T-matrix) and its inverse form are adopted in the mathematical process. A DUT may have three coupled ports in the fields of radio frequency and electromagnetic compatibility. The symmetry in the corresponding S-matrix breaks down, because the numbers of incident and reflected ports are not equal. Thus, it leads to a nonsquare T-matrix by definition. Given that the inverse expression of a nonsquare matrix does not exist, the conventional de-embedding methods are inapplicable for a coupled three-port network. In this article, a de-embedding algorithm, which is feasible for coupled three-port devices, is proposed and verified through the measurement. The proposed de-embedding technique may also be applied on devices with more than three ports.
{"title":"De-Embedding for Coupled Three-Port Devices","authors":"Junyong Park;Yuandong Guo;Bo Pu;DongHyun Kim;Jun Fan","doi":"10.1109/TSIPI.2025.3608692","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3608692","url":null,"abstract":"De-embedding techniques have been introduced to evaluate the real electrical performances of a device under test (DUT), e.g., the traditional thru-reflect-line and short-open-load-thru standards, where the transfer matrix (T-matrix) and its inverse form are adopted in the mathematical process. A DUT may have three coupled ports in the fields of radio frequency and electromagnetic compatibility. The symmetry in the corresponding S-matrix breaks down, because the numbers of incident and reflected ports are not equal. Thus, it leads to a nonsquare T-matrix by definition. Given that the inverse expression of a nonsquare matrix does not exist, the conventional de-embedding methods are inapplicable for a coupled three-port network. In this article, a de-embedding algorithm, which is feasible for coupled three-port devices, is proposed and verified through the measurement. The proposed de-embedding technique may also be applied on devices with more than three ports.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"185-190"},"PeriodicalIF":0.0,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-07DOI: 10.1109/TSIPI.2025.3596886
Anuj Kumar;Jai Narayan Tripathi
This article presents novel observations on the impact of ground-bounce noise (GBN) on logic-HIGH in high-speed digital design. While the impact of power supply noise on logic-HIGH is undeniable and comprehensively studied in the literature, the impact of ground bounce is perceived, as well as the analysis is majorly focused on logic-LOW. This work demonstrates and analyses the impact of GBN on logic-HIGH. The observations are supported by a theoretical investigation using both the analytical and small-signal approaches. Several examples are presented to validate the novel observations considering both the simulation and measurement-based case studies. The simulation-based case studies are presented using several complementary metal oxide semiconductor technologies and measurement-based case studies are performed using standard inverter integrated circuits. There is a close correlation observed between the practical observations and the corresponding theoretical developments.
{"title":"Novel Observations on Impact of Ground Bounce on Logic-HIGH","authors":"Anuj Kumar;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2025.3596886","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3596886","url":null,"abstract":"This article presents novel observations on the impact of ground-bounce noise (GBN) on logic-HIGH in high-speed digital design. While the impact of power supply noise on logic-HIGH is undeniable and comprehensively studied in the literature, the impact of ground bounce is perceived, as well as the analysis is majorly focused on logic-LOW. This work demonstrates and analyses the impact of GBN on logic-HIGH. The observations are supported by a theoretical investigation using both the analytical and small-signal approaches. Several examples are presented to validate the novel observations considering both the simulation and measurement-based case studies. The simulation-based case studies are presented using several complementary metal oxide semiconductor technologies and measurement-based case studies are performed using standard inverter integrated circuits. There is a close correlation observed between the practical observations and the corresponding theoretical developments.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"176-184"},"PeriodicalIF":0.0,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144896775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-26DOI: 10.1109/TSIPI.2025.3583657
Junyong Park;Yuandong Guo;Xiaoning Ye;DongHyun Kim
Far-end crosstalk (FEXT) in typical high-speed printed circuit board striplines is primarily attributed to dielectric inhomogeneity. In this article, the inhomogeneity problem is comprehensively addressed by a novel algorithm that characterizes the dielectric constants (DKs) of glass fibers and epoxy resin. In contrast to other methods, the proposed approach enables one to assess the impact of geometrical parameters on stripline FEXT and to estimate DKcore and DKprepreg based on DKglass and DKresin values extracted through analytical expressions. Full-wave simulations and real-board measurements are conducted to verify the proposed approach.
{"title":"Extraction of DKglass and DKresin for PCB Striplines and Analysis of Far-End Crosstalk","authors":"Junyong Park;Yuandong Guo;Xiaoning Ye;DongHyun Kim","doi":"10.1109/TSIPI.2025.3583657","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3583657","url":null,"abstract":"Far-end crosstalk (FEXT) in typical high-speed printed circuit board striplines is primarily attributed to dielectric inhomogeneity. In this article, the inhomogeneity problem is comprehensively addressed by a novel algorithm that characterizes the dielectric constants (DKs) of glass fibers and epoxy resin. In contrast to other methods, the proposed approach enables one to assess the impact of geometrical parameters on stripline FEXT and to estimate DK<sub>core</sub> and DK<sub>prepreg</sub> based on DK<sub>glass</sub> and DK<sub>resin</sub> values extracted through analytical expressions. Full-wave simulations and real-board measurements are conducted to verify the proposed approach.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"149-155"},"PeriodicalIF":0.0,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144572971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-17DOI: 10.1109/TSIPI.2025.3580490
Jie Li;Min Tang;Junfa Mao
In this article, a hybrid approach combining the boundary element method (BEM) with analytical solution of stacked dielectrics is proposed for the capacitance extraction of multilayer dielectric structures. First, the flexible BEM employs an adaptive refined mesh to address the interconnect region, which contains complex conductors and conformal dielectrics. Second, for the upper and lower stacked dielectrics, the analytical solution based on separation of variables technique is derived to construct interface equations. After that, these equations are treated as the numerical boundary conditions and incorporated into the matrix equation formed by the BEM in the interconnect region. By this means, the proposed hybrid boundary element and analytical method efficiently compresses the regular stacked dielectrics into interface equations through analytical expressions, ensuring high accuracy without introducing additional errors. Furthermore, the numerical discretization is confined to the interconnect region, greatly reducing the number of unknowns and resulting in significant savings in computational resources. Numerical examples validate the accuracy and efficiency of the proposed method.
{"title":"A Hybrid Boundary Element and Analytical Method (BEAM) for Efficient Capacitance Extraction in Multilayer Dielectrics","authors":"Jie Li;Min Tang;Junfa Mao","doi":"10.1109/TSIPI.2025.3580490","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3580490","url":null,"abstract":"In this article, a hybrid approach combining the boundary element method (BEM) with analytical solution of stacked dielectrics is proposed for the capacitance extraction of multilayer dielectric structures. First, the flexible BEM employs an adaptive refined mesh to address the interconnect region, which contains complex conductors and conformal dielectrics. Second, for the upper and lower stacked dielectrics, the analytical solution based on separation of variables technique is derived to construct interface equations. After that, these equations are treated as the numerical boundary conditions and incorporated into the matrix equation formed by the BEM in the interconnect region. By this means, the proposed hybrid boundary element and analytical method efficiently compresses the regular stacked dielectrics into interface equations through analytical expressions, ensuring high accuracy without introducing additional errors. Furthermore, the numerical discretization is confined to the interconnect region, greatly reducing the number of unknowns and resulting in significant savings in computational resources. Numerical examples validate the accuracy and efficiency of the proposed method.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"141-148"},"PeriodicalIF":0.0,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144524419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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