Pub Date : 2025-01-27DOI: 10.1109/TSIPI.2025.3533060
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2025.3533060","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3533060","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854552","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-27DOI: 10.1109/TSIPI.2025.3534910
{"title":"2024 Index IEEE Transactions on Signal and Power Integrity Vol. 3","authors":"","doi":"10.1109/TSIPI.2025.3534910","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3534910","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854991","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TSIPI.2025.3527436
Pranay Vuppunutala;Xiaolu Zhu;Junyong Park;Keith B. Hardin;Zachary C. N. Kratzer;John T. Fessler;Biyao Zhao;Siqi Bai
The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, Z-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy.
{"title":"System-Level Application of the Z-Directed Component (ZDC) for Power Integrity","authors":"Pranay Vuppunutala;Xiaolu Zhu;Junyong Park;Keith B. Hardin;Zachary C. N. Kratzer;John T. Fessler;Biyao Zhao;Siqi Bai","doi":"10.1109/TSIPI.2025.3527436","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3527436","url":null,"abstract":"The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, <italic>Z</i>-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"10-18"},"PeriodicalIF":0.0,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TSIPI.2025.3527437
Yifan Ding;Jianmin Zhang;Ming-Feng Xue;Xin Hua;Benjamin Leung;Eric A. MacIntosh;Chulsoon Hwang
In this article, a multiphysics modeling methodology is presented for predicting the acoustic noise induced by a multilayer ceramic capacitor (MLCC) in mobile electronic devices. The modeling process involves using a prescribed methodology to extract the equivalent source at the resonance frequencies of a printed circuit board (PCB) and then deriving the broadband source multiphysics electrical input mechanical output (EIMO) model. Subsequently, the obtained EIMO model is integrated into PCB vibration simulations, and the resulting vibration data are used for acoustic simulations. The predicted A-weighted sound pressure level excited by the MLCC EIMO model accurately represented the acoustic noise generated by a tested MLCC, achieving a correlation with measurements of 2 dB difference at resonant modes. This approach offers insights into mitigating MLCC-induced acoustic noise in electronic systems and facilitates more effective design strategies.
{"title":"Multilayer Ceramic Capacitor Source Model Application in Acoustic Noise Prediction","authors":"Yifan Ding;Jianmin Zhang;Ming-Feng Xue;Xin Hua;Benjamin Leung;Eric A. MacIntosh;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3527437","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3527437","url":null,"abstract":"In this article, a multiphysics modeling methodology is presented for predicting the acoustic noise induced by a multilayer ceramic capacitor (MLCC) in mobile electronic devices. The modeling process involves using a prescribed methodology to extract the equivalent source at the resonance frequencies of a printed circuit board (PCB) and then deriving the broadband source multiphysics electrical input mechanical output (EIMO) model. Subsequently, the obtained EIMO model is integrated into PCB vibration simulations, and the resulting vibration data are used for acoustic simulations. The predicted A-weighted sound pressure level excited by the MLCC EIMO model accurately represented the acoustic noise generated by a tested MLCC, achieving a correlation with measurements of 2 dB difference at resonant modes. This approach offers insights into mitigating MLCC-induced acoustic noise in electronic systems and facilitates more effective design strategies.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"19-23"},"PeriodicalIF":0.0,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TSIPI.2024.3507712
Kai Li;Chiu-Chih Chou;Wei-Da Kuo;Hao-Hsiang Chuang;Hsin-Chan Hsieh;Ruey-Beei Wu
Double data rate (DDR) memory interface is used in an increasing number of electronic products to increase the efficiency of memory access. Factors such as signal propagation delay, reflection, and crosstalk need to be considered for signal integrity design. This study derives the transfer function of a single transmission line under mismatched boundary conditions and extends it to multiple coupled transmission lines. By utilizing inverse Fourier transform, the pulse responses are obtained and, based on peak distortion analysis, the worst-case eye height and eye width are quickly extracted, saving time in the simulation and achieving high accuracy for the design of high-speed DDR memory interface.
{"title":"Analytic Method of Fast Eye-Diagram Index for Multiple Coupled Lines in DDR","authors":"Kai Li;Chiu-Chih Chou;Wei-Da Kuo;Hao-Hsiang Chuang;Hsin-Chan Hsieh;Ruey-Beei Wu","doi":"10.1109/TSIPI.2024.3507712","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3507712","url":null,"abstract":"Double data rate (DDR) memory interface is used in an increasing number of electronic products to increase the efficiency of memory access. Factors such as signal propagation delay, reflection, and crosstalk need to be considered for signal integrity design. This study derives the transfer function of a single transmission line under mismatched boundary conditions and extends it to multiple coupled transmission lines. By utilizing inverse Fourier transform, the pulse responses are obtained and, based on peak distortion analysis, the worst-case eye height and eye width are quickly extracted, saving time in the simulation and achieving high accuracy for the design of high-speed DDR memory interface.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"226-234"},"PeriodicalIF":0.0,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a novel planar balanced full-passband linear-phase dual-port absorptive filter is presented for the application of signal integrity in balanced systems. To absorb out-of-band reflected wave energy to prevent it from damaging the performance of neighboring active nonlinear circuits, the reflectionless characteristic of the dual-port absorptive filter is realized by loading absorptive networks at both the input and output ports. Negative group delay (NGD) equalized circuits are employed to compensate for salient group delay on both the edges of the passband achieving full-passband linear-phase characteristics. In order to solve the impedance mismatch problem caused by absorption networks and NGD equalized circuits, a quarter-wavelength impedance transformer is introduced to provide good matching characteristics. To verify the design concept, a conventional two-order balanced filter is improved into a full-passband linear-phase dual-port absorptive prototype, which is manufactured and measured with a center frequency of 2.45 GHz.
{"title":"Planar Balanced Full-Passband Linear-Phase Dual-Port Absorptive Filter Based on Negative Group Delay Equalized Compensation","authors":"Shipeng Zhao;Zhongbao Wang;Hongmei Liu;Shaojun Fang","doi":"10.1109/TSIPI.2024.3511497","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3511497","url":null,"abstract":"In this article, a novel planar balanced full-passband linear-phase dual-port absorptive filter is presented for the application of signal integrity in balanced systems. To absorb out-of-band reflected wave energy to prevent it from damaging the performance of neighboring active nonlinear circuits, the reflectionless characteristic of the dual-port absorptive filter is realized by loading absorptive networks at both the input and output ports. Negative group delay (NGD) equalized circuits are employed to compensate for salient group delay on both the edges of the passband achieving full-passband linear-phase characteristics. In order to solve the impedance mismatch problem caused by absorption networks and NGD equalized circuits, a quarter-wavelength impedance transformer is introduced to provide good matching characteristics. To verify the design concept, a conventional two-order balanced filter is improved into a full-passband linear-phase dual-port absorptive prototype, which is manufactured and measured with a center frequency of 2.45 GHz.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"219-225"},"PeriodicalIF":0.0,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-02DOI: 10.1109/TSIPI.2024.3509800
Yingcong Zhang;Guoan Wang
This article proposes a novel structure of coupled line with embedded metasurface aimed at mitigating far-end crosstalk (FEXT) in high-speed data transmission. The square loop metasurface structure is implemented under the coupled line to increase the mutual capacitance between signal traces, thereby mitigating FEXT in the coupled line. The capacitance and the inductance matrices of both conventional coupled line and the proposed metasurface-embedded structure are extracted with numerical equations from the simulations and applied to the equivalent circuit model to comprehensively analyze and accurately evaluate the proposed structure. To validate the design efficacy of the proposed concept, prototypes of conventional and the proposed coupled line structure are implemented on a FR-4 printed circuit board, and their performance in both frequency domain and time domain are measured and compared. Compared to conventional coupled line, experimental results demonstrate that the proposed metasurface embedded coupled line structure significantly enhances the FEXT performance while ensuring robust high-speed signal propagation along the signal traces. Specifically, FEXT is reduced by 8.2 dB within the frequency range of 1–12 GHz, and with the largest improvement of 42.84 dB at 10.9 GHz. This superior FEXT performance coupled with ultra-low latency underscores the significant potential of the proposed metasurface embedded coupled line structure for application in miniaturized high-speed systems.
{"title":"High Signal Integrity Interconnects Embedded With Metasurface for Far-End Crosstalk Reduction and High-Speed Data Transfer","authors":"Yingcong Zhang;Guoan Wang","doi":"10.1109/TSIPI.2024.3509800","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3509800","url":null,"abstract":"This article proposes a novel structure of coupled line with embedded metasurface aimed at mitigating far-end crosstalk (FEXT) in high-speed data transmission. The square loop metasurface structure is implemented under the coupled line to increase the mutual capacitance between signal traces, thereby mitigating FEXT in the coupled line. The capacitance and the inductance matrices of both conventional coupled line and the proposed metasurface-embedded structure are extracted with numerical equations from the simulations and applied to the equivalent circuit model to comprehensively analyze and accurately evaluate the proposed structure. To validate the design efficacy of the proposed concept, prototypes of conventional and the proposed coupled line structure are implemented on a FR-4 printed circuit board, and their performance in both frequency domain and time domain are measured and compared. Compared to conventional coupled line, experimental results demonstrate that the proposed metasurface embedded coupled line structure significantly enhances the FEXT performance while ensuring robust high-speed signal propagation along the signal traces. Specifically, FEXT is reduced by 8.2 dB within the frequency range of 1–12 GHz, and with the largest improvement of 42.84 dB at 10.9 GHz. This superior FEXT performance coupled with ultra-low latency underscores the significant potential of the proposed metasurface embedded coupled line structure for application in miniaturized high-speed systems.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"212-218"},"PeriodicalIF":0.0,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-28DOI: 10.1109/TSIPI.2024.3505141
Xiao-Pei Zhou;Da-Wei Wang;Wen-Sheng Zhao;Peng Zhang;Jia-Hao Pan
In this article, the application of through-silicon capacitor (TSC) in the power distribution network (PDN) of three-dimensional (3-D) integrated circuits (ICs) is systematically investigated for the first time. Additionally, the deep reinforcement learning (DRL) algorithm is integrated to minimize the deployment of TSCs while achieving the target impedance, thereby reducing the cost in practical applications. By selectively replacing the specified through-silicon vias (TSV) with TSCs in the existing TSV array, this method not only ensures uniform stress distribution within the structure but also effectively reduces the required area for decoupling capacitors and enables greater flexibility in TSC applications. A comprehensive investigation is carried out to assess the electrical characteristics of TSCs and their efficiency in mitigating PDN impedance. Then, an advanced approach, combining vector fitting and neural networks, is employed for the parametric modeling of TSCs. The impedance of PDN in 3-D IC is computed using transmission matrix method. By incorporating 3-D IC PDN and TSC information as inputs, the DRL algorithm determines the optimal placement and types of TSCs. The impedance suppression effect of TSC in 3-D IC PDN is verified through various test cases, and the optimization results of DRL were compared with those of other intelligent algorithms. Finally, a comparative analysis was carried out, highlighting the significance of this article.
本文首次系统地研究了通硅电容（TSC）在三维集成电路配电网（PDN）中的应用。此外，集成了深度强化学习（DRL）算法，在实现目标阻抗的同时最大限度地减少了tsc的部署，从而降低了实际应用中的成本。该方法通过选择性地将现有TSV阵列中指定的通硅通孔（TSV）替换为TSC，不仅保证了结构内应力分布均匀，而且有效地减少了去耦电容器所需的面积，使TSC应用具有更大的灵活性。进行了全面的调查，以评估tsc的电特性及其在减轻PDN阻抗方面的效率。然后，采用向量拟合和神经网络相结合的先进方法对tsc进行参数化建模。采用传输矩阵法计算了三维集成电路中PDN的阻抗。DRL算法通过将3-D IC PDN和TSC信息作为输入，确定TSC的最佳位置和类型。通过各种测试用例验证了TSC在三维IC PDN中的阻抗抑制效果，并将DRL的优化结果与其他智能算法的优化结果进行了比较。最后进行了对比分析，凸显了本文的意义。
{"title":"Modeling of Through-Silicon Capacitor and Its Applications for the Optimization of Power Distribution Network in 3-D Integrated Circuits","authors":"Xiao-Pei Zhou;Da-Wei Wang;Wen-Sheng Zhao;Peng Zhang;Jia-Hao Pan","doi":"10.1109/TSIPI.2024.3505141","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3505141","url":null,"abstract":"In this article, the application of through-silicon capacitor (TSC) in the power distribution network (PDN) of three-dimensional (3-D) integrated circuits (ICs) is systematically investigated for the first time. Additionally, the deep reinforcement learning (DRL) algorithm is integrated to minimize the deployment of TSCs while achieving the target impedance, thereby reducing the cost in practical applications. By selectively replacing the specified through-silicon vias (TSV) with TSCs in the existing TSV array, this method not only ensures uniform stress distribution within the structure but also effectively reduces the required area for decoupling capacitors and enables greater flexibility in TSC applications. A comprehensive investigation is carried out to assess the electrical characteristics of TSCs and their efficiency in mitigating PDN impedance. Then, an advanced approach, combining vector fitting and neural networks, is employed for the parametric modeling of TSCs. The impedance of PDN in 3-D IC is computed using transmission matrix method. By incorporating 3-D IC PDN and TSC information as inputs, the DRL algorithm determines the optimal placement and types of TSCs. The impedance suppression effect of TSC in 3-D IC PDN is verified through various test cases, and the optimization results of DRL were compared with those of other intelligent algorithms. Finally, a comparative analysis was carried out, highlighting the significance of this article.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"199-211"},"PeriodicalIF":0.0,"publicationDate":"2024-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142797929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-07DOI: 10.1109/TSIPI.2024.3493817
Aditya Rao;Eric Bogatin;Melinda Piket-May;Mohammed F. Hadi
This article details the impact of non-TEM propagation on a microstrip structure's crosstalk, impedance, and effective dielectric constant. A new onset frequency is defined to quantify where non-TEM dispersion is significant in microstrip transmission lines for high-speed digital applications. The impact of non-TEM dispersion on eye diagrams for digital signals is explored, showing a significant impact from non-TEM dispersion. Using this analysis, guidelines have been defined for when a full-wave simulator must be utilized to simulate a microstrip structure and when a quasi-static simulator provides accurate results at a given data rate.
本文详细介绍了非 TEM 传播对微带结构的串扰、阻抗和有效介电常数的影响。文章定义了一个新的起始频率，以量化高速数字应用中微带传输线的非 TEM 色散显著性。探讨了非 TEM 色散对数字信号眼图的影响，显示了非 TEM 色散的重大影响。通过这一分析，确定了何时必须使用全波模拟器模拟微带结构，以及何时准静态模拟器可在给定数据速率下提供准确结果的指导原则。
{"title":"Non-TEM Dispersion in Microstrip Structures at High Data Rates","authors":"Aditya Rao;Eric Bogatin;Melinda Piket-May;Mohammed F. Hadi","doi":"10.1109/TSIPI.2024.3493817","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3493817","url":null,"abstract":"This article details the impact of non-TEM propagation on a microstrip structure's crosstalk, impedance, and effective dielectric constant. A new onset frequency is defined to quantify where non-TEM dispersion is significant in microstrip transmission lines for high-speed digital applications. The impact of non-TEM dispersion on eye diagrams for digital signals is explored, showing a significant impact from non-TEM dispersion. Using this analysis, guidelines have been defined for when a full-wave simulator must be utilized to simulate a microstrip structure and when a quasi-static simulator provides accurate results at a given data rate.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"178-185"},"PeriodicalIF":0.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-04DOI: 10.1109/TSIPI.2024.3490512
Jack Juang;Ling Zhang;Haran Manoharan;Francesco De Paulis;Chulsoon Hwang
In power distribution network designs, a large number of decoupling capacitors (decaps) may be needed to satisfy target impedance limits. Many algorithms have been proposed and implemented for finding the optimal decap placement, including genetic algorithms (GA), and machine learning methods. In this work, an improved GA is proposed for finding the decap placement pattern that can satisfy a target impedance using the minimum number of decaps. The distribution of capacitors expected to appear in the global minimum solution is first predicted by determining how effective each decap type is toward satisfying certain critical impedance points. This estimation is used to inform the generation of initial solutions in order to put the initial search space nearer the global minimum and ensure certain solution characteristics appear. GA search using this improved population generation is found to be an improvement over a Canonical GA implementation, by finding solutions where the latter could not, or finding a solution using fewer decaps.
在配电网络设计中，可能需要大量去耦电容器（decap）来满足目标阻抗限制。人们提出并实施了许多算法，包括遗传算法（GA）和机器学习方法，用于寻找最佳的去耦电容器位置。在这项工作中，我们提出了一种改进的遗传算法，用于寻找能够满足目标阻抗的去盖帽放置模式，并使用最少的去盖帽数量。首先，通过确定每种分路器类型对满足某些临界阻抗点的有效性，来预测预计会出现在全局最小解决方案中的电容器分布。这种估算用于生成初始解决方案，以便使初始搜索空间更接近全局最小值，并确保出现某些解决方案特征。使用这种改进的种群生成方法进行 GA 搜索，发现比 Canonical GA 实施方法有了改进，可以找到后者无法找到的解决方案，或使用更少的分封点找到解决方案。
{"title":"Augmented Genetic Algorithm for Decoupling Capacitor Optimization in Power Distribution Network Design Through Improved Population Generation","authors":"Jack Juang;Ling Zhang;Haran Manoharan;Francesco De Paulis;Chulsoon Hwang","doi":"10.1109/TSIPI.2024.3490512","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3490512","url":null,"abstract":"In power distribution network designs, a large number of decoupling capacitors (decaps) may be needed to satisfy target impedance limits. Many algorithms have been proposed and implemented for finding the optimal decap placement, including genetic algorithms (GA), and machine learning methods. In this work, an improved GA is proposed for finding the decap placement pattern that can satisfy a target impedance using the minimum number of decaps. The distribution of capacitors expected to appear in the global minimum solution is first predicted by determining how effective each decap type is toward satisfying certain critical impedance points. This estimation is used to inform the generation of initial solutions in order to put the initial search space nearer the global minimum and ensure certain solution characteristics appear. GA search using this improved population generation is found to be an improvement over a Canonical GA implementation, by finding solutions where the latter could not, or finding a solution using fewer decaps.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"186-198"},"PeriodicalIF":0.0,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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