Thermally-aware circuit model and performance analysis of MLGNR for nano-interconnect application

IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Analog Integrated Circuits and Signal Processing Pub Date : 2024-02-21 DOI:10.1007/s10470-024-02254-3
Himanshu Sharma, Karmjit Singh Sandha
{"title":"Thermally-aware circuit model and performance analysis of MLGNR for nano-interconnect application","authors":"Himanshu Sharma,&nbsp;Karmjit Singh Sandha","doi":"10.1007/s10470-024-02254-3","DOIUrl":null,"url":null,"abstract":"<div><p>This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"120 1","pages":"71 - 81"},"PeriodicalIF":1.2000,"publicationDate":"2024-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-024-02254-3","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
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Abstract

This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node.

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用于纳米互连应用的热感知电路模型和 MLGNR 性能分析
本文探讨了温度对多层石墨烯纳米带(MLGNR)散射机制的影响。本文提出了一个热感知电气 ESC 模型以及数学计算,用于评估寄生,并报告了在 16 纳米、22 纳米和 32 纳米技术节点的全局互连长度下,MLGNR 在功率耗散、延迟和功率延迟积 (PDP) 方面随温度变化而变化的性能分析。研究结果表明,随着温度的升高,GNR 互连的平均自由路径会急剧下降,这进一步影响了其在所有三个技术节点的不同全局长度(500-2000 μm)下的自身电阻。我们使用集成电路(SPICE)仿真工具来估算和比较 MLGNR 在三种不同技术节点下的功率耗散、信号延迟和 PDP 性能。结果表明,对于深亚微米技术节点(16、22 和 32 纳米),在 200 至 500 K 的温度范围内,长互连(2000 μm)的传播延迟和 PDP 会增加。此外,基于 ITRS 2013,在 MLGNR 的 200-500 K 温度范围内,16 纳米技术节点的全局互连长度(2000 μm)获得了分析和模拟结果。模拟和分析结果表明,两个模型的结果非常相似。模型的趋势显示,随着温度水平(200-500 K)的增加,16 纳米技术节点的延迟也在增加。
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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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