Bus Admittance Matrix Revisited: Performance Challenges on Modern Computers

Abstract

Bus admittance matrix is widely used in power engineering for network modeling. Being highly sparse, it requires fewer CPU operations when used for calculations. Meanwhile, sparse matrix calculations involve numerous indexing and scalar operations, which are unfavorable to modern processors. Without using the admittance matrix, nodal power injections and the corresponding sparse Jacobian can be computed by an element-wise method, which consists of a highly regular, vectorized evaluation step and a reduction step. This paper revisits the computational performance of the admittance matrix-based method, in terms of power injection and Jacobian matrix calculation, by comparing it with the element-wise method. Case studies show that the admittance matrix method is generally slower than the element-wise method for grid test cases with thousands to hundreds of thousands of buses, especially on CPUs with support for wide vector instructions. This paper also analyzes the impact of the width of vector instructions and memory speed to predict the trend for future computers.