Xingxuan Huang;Dingrui Li;Min Lin;Leon M. Tolbert;Fred Wang;William Giewont
{"title":"Desat Protection With Ultrafast Response for High-Voltage SiC MOSFETs With High dv/dt","authors":"Xingxuan Huang;Dingrui Li;Min Lin;Leon M. Tolbert;Fred Wang;William Giewont","doi":"10.1109/OJIA.2024.3353309","DOIUrl":null,"url":null,"abstract":"This article presents a desat protection scheme with the ultrafast response for high-voltage (>3.3 kV) SiC MOSFETs. Its working principle is the same as the conventional desat protection designed for high-voltage SiC MOSFETs, yet its blanking time is implemented by fully considering the influence of high negative \n<italic>dv<sub>ds</sub>/dt</i>\n during the fast turn-\n<sc>on</small>\n transient. With the same circuitry as the conventional desat protection, the proposed protection scheme can significantly shorten the response time of the desat protection when it is used to protect high-voltage SiC MOSFETs. In addition, the proposed protection scheme with ultrafast response features strong noise immunity, low-cost, and simple implementation. By taking advantage of the high \n<italic>dv/dt</i>\n during the normal turn-\n<sc>on</small>\n transients, the proposed protection scheme can be even faster when the MOSFET has a faster switching speed. Design details and the response speed analysis under various short circuit faults are presented in detail. A half bridge phase leg based on discrete 10 kV/20 A SiC MOSFETs is built to demonstrate the proposed protection scheme. Experimental results at 6.5 kV validate the ultrafast response (115 ns response time under a hard switching fault, 155 ns response time under a fault under load), and strong noise immunity of the proposed desat protection scheme.","PeriodicalId":100629,"journal":{"name":"IEEE Open Journal of Industry Applications","volume":"5 ","pages":"94-105"},"PeriodicalIF":7.9000,"publicationDate":"2024-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10411019","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of Industry Applications","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10411019/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents a desat protection scheme with the ultrafast response for high-voltage (>3.3 kV) SiC MOSFETs. Its working principle is the same as the conventional desat protection designed for high-voltage SiC MOSFETs, yet its blanking time is implemented by fully considering the influence of high negative
dvds/dt
during the fast turn-
on
transient. With the same circuitry as the conventional desat protection, the proposed protection scheme can significantly shorten the response time of the desat protection when it is used to protect high-voltage SiC MOSFETs. In addition, the proposed protection scheme with ultrafast response features strong noise immunity, low-cost, and simple implementation. By taking advantage of the high
dv/dt
during the normal turn-
on
transients, the proposed protection scheme can be even faster when the MOSFET has a faster switching speed. Design details and the response speed analysis under various short circuit faults are presented in detail. A half bridge phase leg based on discrete 10 kV/20 A SiC MOSFETs is built to demonstrate the proposed protection scheme. Experimental results at 6.5 kV validate the ultrafast response (115 ns response time under a hard switching fault, 155 ns response time under a fault under load), and strong noise immunity of the proposed desat protection scheme.