Radiation-Immune Spintronic Binary Synapse and Neuron for Process-in-Memory Architecture

Abstract

This letter proposes a single event upset (SEU)-hardened task-scheduling logic-in-memory xnor/xor neuron and synapse circuit. Using a C-element and a magnetic tunnel junction enhances immunity against SEU injection. Also, using logic-in-memory architecture eliminates the need to access external memory and decreases power and delay. Furthermore, using a carbon nanotube field-effect transistor leads to lower leakage and static current caused by higher gate control in these transistors. Compared to the state-of-the-art counterparts, the developed design offers at least 31%, 17%, and 3% improvement in power, power delay product, and power delay area product, respectively.