{"title":"A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design","authors":"Hao Su;Yiyuan Cai;Shenghua Zhou;Guangchong Hu;Yu He;Yunfeng Xie;Yuhuan Lin;Chunhui Li;Tianqi Zhao;Jun Lan;Wenhui Wang;Wenxin Li;Feichi Zhou;Xiaoguang Liu;Longyang Lin;Yida Li;Hongyu Yu;Kai Chen","doi":"10.1109/JEDS.2024.3359664","DOIUrl":null,"url":null,"abstract":"This paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold voltage definition by various charges across the MOSFET capacitor while being analytical in its form, therefore, suitable for cryogenic CMOS VLSI design. Consequently, a model covering each and all above characteristics is proposed for the first time. Excellent fit between the model and measurement data from 180-nm bulk foundry devices is shown from room temperature to 4 K.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"859-867"},"PeriodicalIF":2.4000,"publicationDate":"2024-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416243","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10416243/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold voltage definition by various charges across the MOSFET capacitor while being analytical in its form, therefore, suitable for cryogenic CMOS VLSI design. Consequently, a model covering each and all above characteristics is proposed for the first time. Excellent fit between the model and measurement data from 180-nm bulk foundry devices is shown from room temperature to 4 K.
期刊介绍：
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
