Pub Date : 2025-03-21DOI: 10.1109/JEDS.2025.3547035
Anne S. Verhulst
{"title":"Editorial for the J-EDS Special Issue for ESSERC 2024","authors":"Anne S. Verhulst","doi":"10.1109/JEDS.2025.3547035","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547035","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"189-189"},"PeriodicalIF":2.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10936519","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/JEDS.2025.3552171
Woo Jin Baek;Joon Pyo Kim;Song Hyeon Kuk;Juhyuk Park;Hyun Soo Kim;Dae-Myeong Geum;Sang Hyeon Kim
We demonstrate field-effect passivation (FEP) of GaN-based blue $mu $ LEDs by incorporating an additional metal-oxide-semiconductor gate structure on the sidewalls. This approach allows for active control of surface band bending at the sidewalls, thereby modulating carrier trapping and de-trapping. We observe that applying a negative gate voltage $(V_{G})$ facilitates electron de-trapping, leading to a reduction in surface recombination and a corresponding decrease in current, as evidenced by an enhanced external quantum efficiency (EQE). Conversely, applying a positive $V_{G}$ results in the opposite effect.
{"title":"Field-Effect Passivation of GaN-Based Blue Micro-Light-Emitting Diodes","authors":"Woo Jin Baek;Joon Pyo Kim;Song Hyeon Kuk;Juhyuk Park;Hyun Soo Kim;Dae-Myeong Geum;Sang Hyeon Kim","doi":"10.1109/JEDS.2025.3552171","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552171","url":null,"abstract":"We demonstrate field-effect passivation (FEP) of GaN-based blue <inline-formula> <tex-math>$mu $ </tex-math></inline-formula> LEDs by incorporating an additional metal-oxide-semiconductor gate structure on the sidewalls. This approach allows for active control of surface band bending at the sidewalls, thereby modulating carrier trapping and de-trapping. We observe that applying a negative gate voltage <inline-formula> <tex-math>$(V_{G})$ </tex-math></inline-formula> facilitates electron de-trapping, leading to a reduction in surface recombination and a corresponding decrease in current, as evidenced by an enhanced external quantum efficiency (EQE). Conversely, applying a positive <inline-formula> <tex-math>$V_{G}$ </tex-math></inline-formula> results in the opposite effect.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"303-307"},"PeriodicalIF":2.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930472","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, high-performance indium gallium tin oxide (IGTO) and nitrogen (N) doped indium tin oxide (ITO) hetero structured bilayer thin-film transistors (TFTs) are prepared by incorporating an N-doped ITO intercalation layer in single-layer IGTO TFTs. The performance of the IGTO/ITO:N bilayer TFTs is significantly improved compared with single-layer IGTO TFTs, with specific indicators including a field-effect mobility of 32.6 cm2/V$cdot $ s, a subthreshold swing of 201 mV/dec, a threshold voltage shifts of 0.21 V and −0.45 V under ±10 V gate-bias stress. The results show that the performance enhancement is due to the rational design of the bilayer structure, in which the ITO layer functions as a charge-accumulation layer, providing additional electrons. Meanwhile, N doping effectively reduces the oxygen vacancies, thereby decreasing the interfacial trap density, and ultimately enhancing the performance of single-layer IGTO TFTs. Through X-ray photoelectron spectroscopy and low-frequency noise analyses, we further confirmed the positive effects of N doping and bilayer structure on reducing the defective states and enhancing the stability of TFTs. Overall, the strategy presented here is effective for preparing high performance oxide TFTs for potential applications in future optoelectronic displays.
{"title":"Design and Optimization of Bilayer InGaSnO and Nitrogen-Doped InSnO Thin-Film Transistors for Enhanced Mobility and Reliability","authors":"Weijie Jiang;Li Lu;Chenfei Li;Wenyang Zhang;Wenzhao Wang;Guoli Li;Jingli Wang;Xingqiang Liu;Ablat Abliz;Da Wan","doi":"10.1109/JEDS.2025.3552454","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552454","url":null,"abstract":"In this study, high-performance indium gallium tin oxide (IGTO) and nitrogen (N) doped indium tin oxide (ITO) hetero structured bilayer thin-film transistors (TFTs) are prepared by incorporating an N-doped ITO intercalation layer in single-layer IGTO TFTs. The performance of the IGTO/ITO:N bilayer TFTs is significantly improved compared with single-layer IGTO TFTs, with specific indicators including a field-effect mobility of 32.6 cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, a subthreshold swing of 201 mV/dec, a threshold voltage shifts of 0.21 V and −0.45 V under ±10 V gate-bias stress. The results show that the performance enhancement is due to the rational design of the bilayer structure, in which the ITO layer functions as a charge-accumulation layer, providing additional electrons. Meanwhile, N doping effectively reduces the oxygen vacancies, thereby decreasing the interfacial trap density, and ultimately enhancing the performance of single-layer IGTO TFTs. Through X-ray photoelectron spectroscopy and low-frequency noise analyses, we further confirmed the positive effects of N doping and bilayer structure on reducing the defective states and enhancing the stability of TFTs. Overall, the strategy presented here is effective for preparing high performance oxide TFTs for potential applications in future optoelectronic displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"290-296"},"PeriodicalIF":2.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-14DOI: 10.1109/JEDS.2025.3551313
Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin
$0.5~mu $ m enhancement-mode (E-mode) p-GaN $Gamma $ -gate RF HEMT with engineered Mg doping profile in p-GaN layer was studied for high power amplifier application. With high/low Mg doping profile design in p-GaN, the traditional Ti/p-GaN Schottky gate behavior can be transformed to ohmic-gate after 550°C 3 minutes post-gate annealing. The ohmic-gate design of p-GaN HEMT can minimize poole-frenkel (PF) emission thus the flicker noise and current collapse (C.C) can be improved. A better gate-to-channel modulation ability is also obtained due to precipitous C-VG curve of low Mg ($1times 10{^{{19}}}$ cm-3) doping concentration p-GaN layer. The fabricated device achieves a threshold voltage (VTH) of +1.1 V, and shows a low on-resistance (RON) of $1.8~Omega cdot $ mm and an off-state breakdown voltage of 206 V. With the engineered Mg doping profile design, a 70% PAE is achieved together with an output power density of 1W/mm at VDS of 10V.
{"title":"High Power Added Efficiency Enhancement-Mode Γ-Gate RF HEMT With High/Low p-GaN Doping Profile","authors":"Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin","doi":"10.1109/JEDS.2025.3551313","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3551313","url":null,"abstract":"<inline-formula> <tex-math>$0.5~mu $ </tex-math></inline-formula>m enhancement-mode (E-mode) p-GaN <inline-formula> <tex-math>$Gamma $ </tex-math></inline-formula>-gate RF HEMT with engineered Mg doping profile in p-GaN layer was studied for high power amplifier application. With high/low Mg doping profile design in p-GaN, the traditional Ti/p-GaN Schottky gate behavior can be transformed to ohmic-gate after 550°C 3 minutes post-gate annealing. The ohmic-gate design of p-GaN HEMT can minimize poole-frenkel (PF) emission thus the flicker noise and current collapse (C.C) can be improved. A better gate-to-channel modulation ability is also obtained due to precipitous C-VG curve of low Mg (<inline-formula> <tex-math>$1times 10{^{{19}}}$ </tex-math></inline-formula>cm-3) doping concentration p-GaN layer. The fabricated device achieves a threshold voltage (VTH) of +1.1 V, and shows a low on-resistance (RON) of <inline-formula> <tex-math>$1.8~Omega cdot $ </tex-math></inline-formula>mm and an off-state breakdown voltage of 206 V. With the engineered Mg doping profile design, a 70% PAE is achieved together with an output power density of 1W/mm at VDS of 10V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"285-289"},"PeriodicalIF":2.0,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10926554","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with a focus on the time-power-law exponent (n) of $Delta $ Vth and temperature activation energy. A coupling phenomenon between hot-carrier injection (HCI) and negative bias temperature instability (NBTI) effects has been found at elevated temperatures, where HCI-induced self-heating effect (SHE) exacerbated the NBTI effects. Device degradation was found to be closely related to the waveform, frequency, and operating temperature. The quasi-static-approximation (QSA) model built with DC stress test data, was employed for device and circuit degradation predictions, and its limitations and applicability were discussed. Additionally, based on AC test data, the QSA model was used to simulate corrections for device and circuit degradation at corresponding frequencies. The results revealed over-predictions of degradation level by a time factor over 10.
{"title":"Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology","authors":"Meng Li;Xin Xu;Xianghui Li;Yunpeng Li;Yiqun Shi;Qingqing Sun;Hao Zhu","doi":"10.1109/JEDS.2025.3549754","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549754","url":null,"abstract":"This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with a focus on the time-power-law exponent (n) of <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> Vth and temperature activation energy. A coupling phenomenon between hot-carrier injection (HCI) and negative bias temperature instability (NBTI) effects has been found at elevated temperatures, where HCI-induced self-heating effect (SHE) exacerbated the NBTI effects. Device degradation was found to be closely related to the waveform, frequency, and operating temperature. The quasi-static-approximation (QSA) model built with DC stress test data, was employed for device and circuit degradation predictions, and its limitations and applicability were discussed. Additionally, based on AC test data, the QSA model was used to simulate corrections for device and circuit degradation at corresponding frequencies. The results revealed over-predictions of degradation level by a time factor over 10.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"270-277"},"PeriodicalIF":2.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918946","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-10DOI: 10.1109/JEDS.2025.3549721
Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono
A silicon-based image sensor is proposed, incorporating plasmonic diffraction gratings tailored to chief ray angles (CRAs), to enhance near-infrared (NIR) sensitivity improvement over a broad range of incident angles. Under quasi-surface plasmon resonance (quasi-SPR) conditions, the metal grating efficiently diffracted incident light into the silicon absorption layer. The period and width of the metal grating were adjusted at each pixel position according to CRAs, thereby improving the NIR sensitivity at sensor edges. The plasmonically diffracted light with angled chief ray was confined within the pixel photodiode. The photon confinement resulted in a significant improvement in absorption of approximately 37% or more, within an incident angle range of 30 degrees at a NIR wavelength of 940 nm and a silicon thickness of 3 μm. The improvement in NIR absorption over a broad incident angle range enhances the sensitivity of the entire sensor chip, representing a significant advancement for NIR cameras.
{"title":"Enhancement of Near-Infrared Sensitivity in Silicon-Based Image Sensors to Oblique Chief Rays via Quasi-Surface Plasmon Resonance","authors":"Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono","doi":"10.1109/JEDS.2025.3549721","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549721","url":null,"abstract":"A silicon-based image sensor is proposed, incorporating plasmonic diffraction gratings tailored to chief ray angles (CRAs), to enhance near-infrared (NIR) sensitivity improvement over a broad range of incident angles. Under quasi-surface plasmon resonance (quasi-SPR) conditions, the metal grating efficiently diffracted incident light into the silicon absorption layer. The period and width of the metal grating were adjusted at each pixel position according to CRAs, thereby improving the NIR sensitivity at sensor edges. The plasmonically diffracted light with angled chief ray was confined within the pixel photodiode. The photon confinement resulted in a significant improvement in absorption of approximately 37% or more, within an incident angle range of 30 degrees at a NIR wavelength of 940 nm and a silicon thickness of 3 μm. The improvement in NIR absorption over a broad incident angle range enhances the sensitivity of the entire sensor chip, representing a significant advancement for NIR cameras.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"278-284"},"PeriodicalIF":2.0,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918731","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-06DOI: 10.1109/JEDS.2025.3548595
Yeonsil Yang;Jongmin Lee;Jang Hyun Kim
In this paper, we analyze the electrical and thermal characteristics through Drain-Extended Fin Field-effect Transistor (DeFinFET) using separated high-k field plates. In this article, we first compare the structure using silicon dioxide (SiO2) as the field plate near the drain with that using aluminum oxide (Al2O3). The maximum lattice temperature ($T_{max}$ ) in the hafnium oxide (HfO2)/SiO2 structure is 391.953 K under the same current condition, whereas $T_{max}$ is reduced to 360.941 K in the HfO2/Al2O3 structure, indicating improved thermal management. Similarly, the thermal resistance $(R_th)$ is reduced by 8.73% in the Al2O3 based structure, indicating improved thermal characteristics. Heat flux analysis results show that 60.1% of the generated heat is dissipated through the extended drain region, which identifies the heat dissipation path of the device. And when the length of the Al2O3 field plate in the HfO2/Al2O3 structure was changed to 20 nm, 40 nm, 60 nm, and 80 nm, the $R_{mathrm{th}}$ of the 80 nm configuration was found to achieve the best thermal performance with a thermal resistance of 217.091 μm · K/mW. In addition, in this structure, the drain current reduction rate due to SHE was the lowest at 12.1%, and excellent breakdown voltage $(V_{mathrm{BD}})$ was derived because the electric field was not concentrated at the field plate junction near the drain. Consequently, the proposed device has potential application to high voltage (HV) System on Chip (SoC).
{"title":"Thermal Characteristics Enhancement of Drain-Extended FinFETs for System on Chip Applications With Dual High-k Field Plates","authors":"Yeonsil Yang;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2025.3548595","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548595","url":null,"abstract":"In this paper, we analyze the electrical and thermal characteristics through Drain-Extended Fin Field-effect Transistor (DeFinFET) using separated high-k field plates. In this article, we first compare the structure using silicon dioxide (SiO2) as the field plate near the drain with that using aluminum oxide (Al2O3). The maximum lattice temperature (<inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula>) in the hafnium oxide (HfO2)/SiO2 structure is 391.953 K under the same current condition, whereas <inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula> is reduced to 360.941 K in the HfO2/Al2O3 structure, indicating improved thermal management. Similarly, the thermal resistance <inline-formula> <tex-math>$(R_th)$ </tex-math></inline-formula> is reduced by 8.73% in the Al2O3 based structure, indicating improved thermal characteristics. Heat flux analysis results show that 60.1% of the generated heat is dissipated through the extended drain region, which identifies the heat dissipation path of the device. And when the length of the Al2O3 field plate in the HfO2/Al2O3 structure was changed to 20 nm, 40 nm, 60 nm, and 80 nm, the <inline-formula> <tex-math>$R_{mathrm{th}}$ </tex-math></inline-formula> of the 80 nm configuration was found to achieve the best thermal performance with a thermal resistance of 217.091 μm · K/mW. In addition, in this structure, the drain current reduction rate due to SHE was the lowest at 12.1%, and excellent breakdown voltage <inline-formula> <tex-math>$(V_{mathrm{BD}})$ </tex-math></inline-formula> was derived because the electric field was not concentrated at the field plate junction near the drain. Consequently, the proposed device has potential application to high voltage (HV) System on Chip (SoC).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"182-188"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915199","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-06DOI: 10.1109/JEDS.2025.3548886
Chang-Jiun Lai;Ming-Dou Ker
Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events. The development of a novel ESD event detector, integrated on a single chip and featuring a logarithmic amplifier, a magnitude discriminator, and a time discriminator, has been motivated by this. This detector has been designed and fabricated in a 0.18-$mu $ m CMOS process. The magnitude of the ESD event can be detected and converted to 5-bit digital output codes, whereas the time duration of the ESD event can be converted to 3-bit digital output codes by the newly developed ESD event detector. It has been proven in field applications that the detected ESD events can be successfully transmitted to the ESD control center through the RF Wi-Fi module, enabling real-time ESD monitoring and control in manufacturing environments.
{"title":"Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection","authors":"Chang-Jiun Lai;Ming-Dou Ker","doi":"10.1109/JEDS.2025.3548886","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548886","url":null,"abstract":"Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events. The development of a novel ESD event detector, integrated on a single chip and featuring a logarithmic amplifier, a magnitude discriminator, and a time discriminator, has been motivated by this. This detector has been designed and fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process. The magnitude of the ESD event can be detected and converted to 5-bit digital output codes, whereas the time duration of the ESD event can be converted to 3-bit digital output codes by the newly developed ESD event detector. It has been proven in field applications that the detected ESD events can be successfully transmitted to the ESD control center through the RF Wi-Fi module, enabling real-time ESD monitoring and control in manufacturing environments.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"252-262"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915207","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Corrections to “Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure”","authors":"Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka","doi":"10.1109/JEDS.2025.3542189","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542189","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"134-134"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10913980","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-04DOI: 10.1109/JEDS.2025.3547860
Dae-Young Jeon;So Jeong Park;Sebastian Pregl;Jens Trommer;André Heinzig;Thomas Mikolajick;Walter M. Weber
Schottky-barrier (SB) transistors show great potential as advanced transistors for meeting power, performance, area, and cost requirements. In this study, the dominant transport mechanisms of SB Si-nanowire (NW) transistors were investigated with respect to channel length for accurate performance estimation and to provide key insights for practical applications. Evaluations of the temperature-dependent drain current, transconductance, and activation energy from SB Si-NW transistors revealed that the SB-dominant thermionic effect competes with Si-NW channel-limited conduction when the initial SB height is relatively low. Moreover, the Si-NW channel length was sufficiently long to dominate the total resistance, overcoming resistance effects arising from the SB.
{"title":"Channel Length Dependence of Effective Barrier Height Experienced by Charge Carriers in Schottky-Barrier Transistors Based on Si-Nanowire Arrays","authors":"Dae-Young Jeon;So Jeong Park;Sebastian Pregl;Jens Trommer;André Heinzig;Thomas Mikolajick;Walter M. Weber","doi":"10.1109/JEDS.2025.3547860","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547860","url":null,"abstract":"Schottky-barrier (SB) transistors show great potential as advanced transistors for meeting power, performance, area, and cost requirements. In this study, the dominant transport mechanisms of SB Si-nanowire (NW) transistors were investigated with respect to channel length for accurate performance estimation and to provide key insights for practical applications. Evaluations of the temperature-dependent drain current, transconductance, and activation energy from SB Si-NW transistors revealed that the SB-dominant thermionic effect competes with Si-NW channel-limited conduction when the initial SB height is relatively low. Moreover, the Si-NW channel length was sufficiently long to dominate the total resistance, overcoming resistance effects arising from the SB.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"168-172"},"PeriodicalIF":2.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909662","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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