Pub Date : 2026-02-24DOI: 10.1109/JEDS.2026.3667184
Thi Thanh Huong Vu;Kevin M. Batenburg;Antonius A. I. Aarnink;Weihua Wu;Alexey Y. Kovalgin;Dirk J. Gravesteijn;Raymond J. E. Hueting
For applications such as photodetection and electron microscopy, adopting ultra-shallow pn-junction diodes with ultra-low saturation currents is crucial. One way to realize such diodes is by employing an ultra-thin boron layer $text {(}{sim }2-10$ nm) on top of n-type silicon (Si), i.e., the boron/Si diode. So far, for relatively low process temperatures $text {(}Tleq 400^{circ }$ C) typically used in standard IC/CMOS processes, the boron/Si interface has not been formed in a controllable way. In this work, through an extensive in-depth growth study, we have developed a two-step growth method for the boron formation for a batch furnace, based on the assumption that the nucleation layer for growing boron is formed at $T=250^{circ }$ C, and subsequently, a higher temperature $text {(}T=400^{circ }$ C) is used for a final rapid deposition of boron in a batch furnace. This approach enables precise control over the growth of thin boron layers. A long deposition at $250~^{circ }$ C leads to the formation of a continuous boron layer, significantly reducing the surface roughness and lowering the incubation time at $T=400^{circ }$ C. The improved boron coverage has a direct impact on the ideality factor $text {(}eta text {)}$ and saturation current density $J_{textrm {s}}$ , crucial for the boron/Si diode. As a result, for fully metallized structures a reproducibly low $J_{textrm {s}}$ of $sim 4.32cdot 10^{-16}$ A/$mu $ m2 has been achieved, with an ideality factor of $eta ~approx ~1.02$ , and a barrier height $Phi _{textrm {B}}$ , i.e., a measure of the interface charge that induces the ultrashallow p+ layer, of ~0.84 V.
{"title":"Realization of Pure Boron/Si Diodes Through a Two-Step Low-Temperature Growth in a Home-Built LP CVD System","authors":"Thi Thanh Huong Vu;Kevin M. Batenburg;Antonius A. I. Aarnink;Weihua Wu;Alexey Y. Kovalgin;Dirk J. Gravesteijn;Raymond J. E. Hueting","doi":"10.1109/JEDS.2026.3667184","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3667184","url":null,"abstract":"For applications such as photodetection and electron microscopy, adopting ultra-shallow pn-junction diodes with ultra-low saturation currents is crucial. One way to realize such diodes is by employing an ultra-thin boron layer <inline-formula> <tex-math>$text {(}{sim }2-10$ </tex-math></inline-formula>nm) on top of n-type silicon (Si), i.e., the boron/Si diode. So far, for relatively low process temperatures <inline-formula> <tex-math>$text {(}Tleq 400^{circ }$ </tex-math></inline-formula>C) typically used in standard IC/CMOS processes, the boron/Si interface has not been formed in a controllable way. In this work, through an extensive in-depth growth study, we have developed a two-step growth method for the boron formation for a batch furnace, based on the assumption that the nucleation layer for growing boron is formed at <inline-formula> <tex-math>$T=250^{circ }$ </tex-math></inline-formula>C, and subsequently, a higher temperature <inline-formula> <tex-math>$text {(}T=400^{circ }$ </tex-math></inline-formula>C) is used for a final rapid deposition of boron in a batch furnace. This approach enables precise control over the growth of thin boron layers. A long deposition at <inline-formula> <tex-math>$250~^{circ }$ </tex-math></inline-formula>C leads to the formation of a continuous boron layer, significantly reducing the surface roughness and lowering the incubation time at <inline-formula> <tex-math>$T=400^{circ }$ </tex-math></inline-formula>C. The improved boron coverage has a direct impact on the ideality factor <inline-formula> <tex-math>$text {(}eta text {)}$ </tex-math></inline-formula> and saturation current density <inline-formula> <tex-math>$J_{textrm {s}}$ </tex-math></inline-formula>, crucial for the boron/Si diode. As a result, for fully metallized structures a reproducibly low <inline-formula> <tex-math>$J_{textrm {s}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$sim 4.32cdot 10^{-16}$ </tex-math></inline-formula> A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m2 has been achieved, with an ideality factor of <inline-formula> <tex-math>$eta ~approx ~1.02$ </tex-math></inline-formula>, and a barrier height <inline-formula> <tex-math>$Phi _{textrm {B}}$ </tex-math></inline-formula>, i.e., a measure of the interface charge that induces the ultrashallow p+ layer, of ~0.84 V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"176-185"},"PeriodicalIF":2.4,"publicationDate":"2026-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11408807","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-16DOI: 10.1109/JEDS.2026.3665477
Kejun Xia
We previously derived the power spectral density (PSD) of thermal flux fluctuations at low frequencies for a thermal conductor under non-equilibrium conditions, which is relevant for device modeling due to self-heating effects. In this work, we extend the analysis to include frequency dependence. A closed-form expression is obtained for the case of temperature-independent thermal conductivity and heat capacity. The thermal flux PSD can be accurately approximated as $S_{i,T}(f)approx 4k[(T^{2}+T_{a}^{2})Re (Y_{th})/2-(T-T_{a})^{2}G_{th}/6]$ where $k$ is the Boltzmann constant, $Y_{th}$ and $G_{th}$ is the AC and DC thermal admittances, and $T$ and $T_{a}$ are the device and ambient temperatures, respectively. We further demonstrate that a simple one-node RC model, combined with a frequency-independent flux PSD, provides a reasonable approximation for the frequency dependence of the temperature fluctuation PSD.
{"title":"Power Spectral Density of Thermal Noise at High Frequencies in Thermal Conductance for Semiconductor Devices","authors":"Kejun Xia","doi":"10.1109/JEDS.2026.3665477","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3665477","url":null,"abstract":"We previously derived the power spectral density (PSD) of thermal flux fluctuations at low frequencies for a thermal conductor under non-equilibrium conditions, which is relevant for device modeling due to self-heating effects. In this work, we extend the analysis to include frequency dependence. A closed-form expression is obtained for the case of temperature-independent thermal conductivity and heat capacity. The thermal flux PSD can be accurately approximated as <inline-formula> <tex-math>$S_{i,T}(f)approx 4k[(T^{2}+T_{a}^{2})Re (Y_{th})/2-(T-T_{a})^{2}G_{th}/6]$ </tex-math></inline-formula> where <inline-formula> <tex-math>$k$ </tex-math></inline-formula> is the Boltzmann constant, <inline-formula> <tex-math>$Y_{th}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$G_{th}$ </tex-math></inline-formula> is the AC and DC thermal admittances, and <inline-formula> <tex-math>$T$ </tex-math></inline-formula> and <inline-formula> <tex-math>$T_{a}$ </tex-math></inline-formula> are the device and ambient temperatures, respectively. We further demonstrate that a simple one-node RC model, combined with a frequency-independent flux PSD, provides a reasonable approximation for the frequency dependence of the temperature fluctuation PSD.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"159-163"},"PeriodicalIF":2.4,"publicationDate":"2026-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11397504","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147299692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-13DOI: 10.1109/JEDS.2026.3664683
Sayma Nowshin Chowdhury;Alex L. Mazzoni;Xiaohang Zhang;Andreu L. Glasmann;Halid Mulaosmanovic;Stefan Dünkel;Gunda Beernink;Sven Beyer;Sina Najmaei;Sahil Shah
Ferroelectric field-effect transistors (FeFETs) are strong candidates for synaptic devices in neuromorphic and in-memory computing due to their multi-level programmability, non-volatility, and complementary metal-oxide-semiconductor (CMOS) compatibility. In this work, we experimentally demonstrate multi-bit operation of FeFET synapses integrated on GlobalFoundries’ 28nm CMOS process. Specifically, the work uses an incremental pulsing scheme, showing stable access to intermediate polarization states and long-term retention. We further examine the role of device size, read-out gate voltage, and array topology as fundamental design trade-offs, showing that larger-area FeFETs provide more deterministic state programming, while smaller devices favor integration density. Finally, we compare 1-FeFET and nT–1FeFET array architectures with static random-access memory (SRAM), outlining the density, selection, and scalability implications of each. These findings provide both device-level insights and circuit-architecture considerations, guiding the co-design of FeFET-based synaptic arrays for future neuromorphic accelerators.
{"title":"Measurement and Analysis of Multistate Ferroelectric Transistors in 28 nm CMOS Process","authors":"Sayma Nowshin Chowdhury;Alex L. Mazzoni;Xiaohang Zhang;Andreu L. Glasmann;Halid Mulaosmanovic;Stefan Dünkel;Gunda Beernink;Sven Beyer;Sina Najmaei;Sahil Shah","doi":"10.1109/JEDS.2026.3664683","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3664683","url":null,"abstract":"Ferroelectric field-effect transistors (FeFETs) are strong candidates for synaptic devices in neuromorphic and in-memory computing due to their multi-level programmability, non-volatility, and complementary metal-oxide-semiconductor (CMOS) compatibility. In this work, we experimentally demonstrate multi-bit operation of FeFET synapses integrated on GlobalFoundries’ 28nm CMOS process. Specifically, the work uses an incremental pulsing scheme, showing stable access to intermediate polarization states and long-term retention. We further examine the role of device size, read-out gate voltage, and array topology as fundamental design trade-offs, showing that larger-area FeFETs provide more deterministic state programming, while smaller devices favor integration density. Finally, we compare 1-FeFET and nT–1FeFET array architectures with static random-access memory (SRAM), outlining the density, selection, and scalability implications of each. These findings provide both device-level insights and circuit-architecture considerations, guiding the co-design of FeFET-based synaptic arrays for future neuromorphic accelerators.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"164-175"},"PeriodicalIF":2.4,"publicationDate":"2026-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11395490","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-12DOI: 10.1109/JEDS.2026.3664742
M. G. Ancona;C. R. DeVore;S. J. Cooke
Continuum approaches are renowned in mathematical physics for their parsimony, robustness, and numerical efficiency, and for these reasons are especially valuable for physics-based modeling. For this paper the relevant field is semiconductor device engineering where the original continuum description of diffusion-drift theory remains in wide use. However, this theory is known to be inadequate for describing high-field transport, and efforts to improve on it, while having a long history, are generally regarded as phenomenological and useful only when buttressed by extensive experimental characterization. With this as motivation, we develop a new physics-based approach that we call drag history theory using classical field theoretic methods rather than via the traditional route based on the Boltzmann equation. Critical to our theory are various material response functions that we characterize specifically for silicon using Monte Carlo simulations of a high-voltage diode. Most important is the response function for the drag force felt by the electron gas as it flows through the lattice wherein one needs to properly account for its non-instantaneous nature. By weighing the contributions of mechanical and thermal inertia and thermal diffusion, we also discuss the conditions under which the full description can be simplified with significant computational benefits.
{"title":"Continuum Modeling of High-Field Transport in Semiconductors","authors":"M. G. Ancona;C. R. DeVore;S. J. Cooke","doi":"10.1109/JEDS.2026.3664742","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3664742","url":null,"abstract":"Continuum approaches are renowned in mathematical physics for their parsimony, robustness, and numerical efficiency, and for these reasons are especially valuable for physics-based modeling. For this paper the relevant field is semiconductor device engineering where the original continuum description of diffusion-drift theory remains in wide use. However, this theory is known to be inadequate for describing high-field transport, and efforts to improve on it, while having a long history, are generally regarded as phenomenological and useful only when buttressed by extensive experimental characterization. With this as motivation, we develop a new physics-based approach that we call drag history theory using classical field theoretic methods rather than via the traditional route based on the Boltzmann equation. Critical to our theory are various material response functions that we characterize specifically for silicon using Monte Carlo simulations of a high-voltage diode. Most important is the response function for the drag force felt by the electron gas as it flows through the lattice wherein one needs to properly account for its non-instantaneous nature. By weighing the contributions of mechanical and thermal inertia and thermal diffusion, we also discuss the conditions under which the full description can be simplified with significant computational benefits.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"186-203"},"PeriodicalIF":2.4,"publicationDate":"2026-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11395447","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-09DOI: 10.1109/JEDS.2026.3662337
Haojie Lv;Xiaoqing Yu;Lun Li;Peiyu Zhang
This paper proposes a novel 4H-SiC Photoconductive Semiconductor Switches (PCSS) with anti-reflection function for incident lasers, which depends on an AlN composite anti-reflection coating. The key innovation lies in the graded-index design of the anti-reflection coating, which is fabricated as a laminate of a uniform AlN film and a tilted nanopillar (TN) AlN film via reactive magnetron sputtering combined with Glancing Angle Deposition (GLAD). This mono-material structure not only creates a continuous refractive index transition from air to the 4H-SiC substrate—significantly suppressing Fresnel reflection—but also inherently avoids the interfacial reliability issues associated with conventional heterogeneous multilayer coatings. Measurement shows that, at the incident wavelength of 532 nm, the transmission rate of this coating for PCSS is increased by 65% and 15% compared to no anti-reflection film and single uniform film. Furthermore, the optoelectronic characteristics of PCSS with composite anti-reflection coating are analyzed. It has been found that this PCSS exhibits a very high transient current of 10.3A, and the on-state resistance has been reduced to $17Omega $ when the optical power density of the incident laser is merely 2.5 MW/cm2. The introduction of this flexible composite anti-reflection coating with adjustable refractive index is a very promising solution for the laser absorption efficiency, device miniaturization and frequency improvement of PCSS.
{"title":"Research on 4H-SiC Photoconductive Semiconductor Switch Employing Composite Anti-Reflection Coating","authors":"Haojie Lv;Xiaoqing Yu;Lun Li;Peiyu Zhang","doi":"10.1109/JEDS.2026.3662337","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3662337","url":null,"abstract":"This paper proposes a novel 4H-SiC Photoconductive Semiconductor Switches (PCSS) with anti-reflection function for incident lasers, which depends on an AlN composite anti-reflection coating. The key innovation lies in the graded-index design of the anti-reflection coating, which is fabricated as a laminate of a uniform AlN film and a tilted nanopillar (TN) AlN film via reactive magnetron sputtering combined with Glancing Angle Deposition (GLAD). This mono-material structure not only creates a continuous refractive index transition from air to the 4H-SiC substrate—significantly suppressing Fresnel reflection—but also inherently avoids the interfacial reliability issues associated with conventional heterogeneous multilayer coatings. Measurement shows that, at the incident wavelength of 532 nm, the transmission rate of this coating for PCSS is increased by 65% and 15% compared to no anti-reflection film and single uniform film. Furthermore, the optoelectronic characteristics of PCSS with composite anti-reflection coating are analyzed. It has been found that this PCSS exhibits a very high transient current of 10.3A, and the on-state resistance has been reduced to <inline-formula> <tex-math>$17Omega $ </tex-math></inline-formula> when the optical power density of the incident laser is merely 2.5 MW/cm2. The introduction of this flexible composite anti-reflection coating with adjustable refractive index is a very promising solution for the laser absorption efficiency, device miniaturization and frequency improvement of PCSS.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"137-144"},"PeriodicalIF":2.4,"publicationDate":"2026-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11373718","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-06DOI: 10.1109/JEDS.2026.3661727
Lautaro N. Petrauskas;Anju Kumari R.;Stefan C. B. Mannsfeld;Bahman K. Boroujeni;Frank Ellinger
In this work, a reservoir computing (RC) system implemented with an organic memcapacitor is presented, tailored for energy-efficient time-series classification. The neuromorphic properties of the memory device are shown, and by exploiting them we demonstrate its suitability as a physical reservoir. As a case of study, we implement a system for classification of electrical penetration graph (EPG) signals, which encode the feeding behavior of insects on plant tissues—a critical measure in agricultural pest monitoring. For this task, an accuracy over 93 % is obtained for a reservoir containing eight devices, with an average energy per pulse of 82 pJ per device, showcasing both its high performance and low energy requirement.
{"title":"Memcapacitor-Based Insect Feeding Behaviour Classification With Reservoir Computing","authors":"Lautaro N. Petrauskas;Anju Kumari R.;Stefan C. B. Mannsfeld;Bahman K. Boroujeni;Frank Ellinger","doi":"10.1109/JEDS.2026.3661727","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3661727","url":null,"abstract":"In this work, a reservoir computing (RC) system implemented with an organic memcapacitor is presented, tailored for energy-efficient time-series classification. The neuromorphic properties of the memory device are shown, and by exploiting them we demonstrate its suitability as a physical reservoir. As a case of study, we implement a system for classification of electrical penetration graph (EPG) signals, which encode the feeding behavior of insects on plant tissues—a critical measure in agricultural pest monitoring. For this task, an accuracy over 93 % is obtained for a reservoir containing eight devices, with an average energy per pulse of 82 pJ per device, showcasing both its high performance and low energy requirement.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"151-158"},"PeriodicalIF":2.4,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11372789","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We develop a multi-pulse test for dynamic interface trap characterization in lateral double-diffused MOSFET (LDMOS) devices. By extracting the gate-to-drain charge $(Q_{mathrm { GD}})$ during Miller plateau, the proposed method indicates the quantitative evaluation of the interface trap charge $(Q_{mathrm { it}})$ in the n-drift region under switching conditions. Experimental results reveal that increased interface trap density $(D_{mathrm { it}})$ leads to prolonged switching transitions and elevated $Q_{mathrm { GD}}$ . Besides, increasing the number of pulses enables the extraction of multiple $Q_{mathrm { it}}$ values and their corresponding carrier capture time distributions. Furthermore, varying the test pulse amplitude facilitates selective probing of $D_{mathrm { it}}$ at different trap energy levels $(E_{mathrm { T}})$ . The proposed fast dynamic evaluation technique demonstrates significant potential for interface trap analysis in the n-drift region of power MOSFET devices and provides a practical tool for their reliability assessment.
{"title":"Evaluation of Interface Traps Within Drift Region in LDMOS Using a Multi-Pulse Test Method","authors":"Qianwen Guo;Jiawei Cao;Ke Zhou;Fang Liu;Dongyan Zhao;Yanning Chen;Bo Wu;Yongfeng Deng;Dawei Gao;Xugang Ke;Junkang Li;Rui Zhang","doi":"10.1109/JEDS.2026.3661617","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3661617","url":null,"abstract":"We develop a multi-pulse test for dynamic interface trap characterization in lateral double-diffused MOSFET (LDMOS) devices. By extracting the gate-to-drain charge <inline-formula> <tex-math>$(Q_{mathrm { GD}})$ </tex-math></inline-formula> during Miller plateau, the proposed method indicates the quantitative evaluation of the interface trap charge <inline-formula> <tex-math>$(Q_{mathrm { it}})$ </tex-math></inline-formula> in the n-drift region under switching conditions. Experimental results reveal that increased interface trap density <inline-formula> <tex-math>$(D_{mathrm { it}})$ </tex-math></inline-formula> leads to prolonged switching transitions and elevated <inline-formula> <tex-math>$Q_{mathrm { GD}}$ </tex-math></inline-formula>. Besides, increasing the number of pulses enables the extraction of multiple <inline-formula> <tex-math>$Q_{mathrm { it}}$ </tex-math></inline-formula> values and their corresponding carrier capture time distributions. Furthermore, varying the test pulse amplitude facilitates selective probing of <inline-formula> <tex-math>$D_{mathrm { it}}$ </tex-math></inline-formula> at different trap energy levels <inline-formula> <tex-math>$(E_{mathrm { T}})$ </tex-math></inline-formula>. The proposed fast dynamic evaluation technique demonstrates significant potential for interface trap analysis in the n-drift region of power MOSFET devices and provides a practical tool for their reliability assessment.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"145-150"},"PeriodicalIF":2.4,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11372746","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) feature low ON resistance and low gate-input capacitance, so that they can serves as power switches with switching frequency from several MHz to tens of MHz level. However, GaN HEMTs have nonlinear gate-to-drain junction capacitance $C_{GD}$ which shows large value at low drain-to-source voltage $(v_{ds})$ , causing gate voltage oscillation under large dv/dt of $v_{ds}$ and possible false turn-on (FTN) problem. In this paper, a FTN protection method is proposed to mitigate the gate voltage oscillation by connecting a passive circuit cell to the drain-node of GaN HEMT and suppressing the Miller current flowing through $C_{GD}$ . Following mechanism analysis, the proposed protection technology is verified in a 6.72MHz, 32W Class-E power inverter with commercial p-GaN HEMT device. The results show that the OFF-state gate voltage oscillation amplitude is decreased to 0.5 times of original value after modifying the prototype with the proposed Miller-current suppressing technology. In addition to avoid FTN successfully, the switching speed of GaN HEMT are not affected as well.
{"title":"Miller-Current Suppressing Technology for False Turn-On Protection of Commercial p-GaN HEMTs","authors":"Ziheng Liu;Jiayin He;Hongjie Peng;Ju Gao;Wenbo Xia;Chengkang Ao;Jinyan Wang;Maojun Wang;Jin Wei;Yong Xie","doi":"10.1109/JEDS.2026.3661537","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3661537","url":null,"abstract":"Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) feature low ON resistance and low gate-input capacitance, so that they can serves as power switches with switching frequency from several MHz to tens of MHz level. However, GaN HEMTs have nonlinear gate-to-drain junction capacitance <inline-formula> <tex-math>$C_{GD}$ </tex-math></inline-formula> which shows large value at low drain-to-source voltage <inline-formula> <tex-math>$(v_{ds})$ </tex-math></inline-formula>, causing gate voltage oscillation under large dv/dt of <inline-formula> <tex-math>$v_{ds}$ </tex-math></inline-formula> and possible false turn-on (FTN) problem. In this paper, a FTN protection method is proposed to mitigate the gate voltage oscillation by connecting a passive circuit cell to the drain-node of GaN HEMT and suppressing the Miller current flowing through <inline-formula> <tex-math>$C_{GD}$ </tex-math></inline-formula>. Following mechanism analysis, the proposed protection technology is verified in a 6.72MHz, 32W Class-E power inverter with commercial p-GaN HEMT device. The results show that the OFF-state gate voltage oscillation amplitude is decreased to 0.5 times of original value after modifying the prototype with the proposed Miller-current suppressing technology. In addition to avoid FTN successfully, the switching speed of GaN HEMT are not affected as well.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"113-121"},"PeriodicalIF":2.4,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11372787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-06DOI: 10.1109/JEDS.2026.3661982
Geonhee Shin;Youngkeun Park;Jaejoong Jeong;Heetae Kim;Byung Jin Cho
We demonstrate a charge-trap flash (CTF) device with a germanium-incorporated silicon nitride (Ge:SiN) charge-trap layer (CTL). Compared to a conventional SiN CTL, the 6 nm-thick Ge:SiN CTL exhibits increased trap density and deeper trap levels. As a result, the Ge:SiN device achieves a 34% larger memory window, along with enhanced retention and endurance characteristics. To further validate, we conducted a spatial study at 4 nm-thick CTL by varying the Ge-incorporated region within the CTL, examining both the tunneling oxide proximal ($T_{mathrm {OX}}$ -proximal) Ge:SiN device and the blocking oxide proximal ($B_{mathrm {OX}}$ -proximal) Ge:SiN device. The $B_{mathrm {OX}}$ -proximal Ge:SiN device consistently exhibits memory performance enhancement. These results provide guidelines for the spatial engineering of Ge:SiN CTL, confirming that the memory performance advantages of the Ge incorporation persist down to 4 nm and supporting a $B_{mathrm {OX}}$ -proximal Ge incorporation. The material and spatial engineering demonstrate the potential of Ge:SiN CTL for next generation 3D NAND flash memory.
{"title":"Memory Window Enhancement With Germanium-Incorporated Charge Trap Layer in Flash Memory Device","authors":"Geonhee Shin;Youngkeun Park;Jaejoong Jeong;Heetae Kim;Byung Jin Cho","doi":"10.1109/JEDS.2026.3661982","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3661982","url":null,"abstract":"We demonstrate a charge-trap flash (CTF) device with a germanium-incorporated silicon nitride (Ge:SiN) charge-trap layer (CTL). Compared to a conventional SiN CTL, the 6 nm-thick Ge:SiN CTL exhibits increased trap density and deeper trap levels. As a result, the Ge:SiN device achieves a 34% larger memory window, along with enhanced retention and endurance characteristics. To further validate, we conducted a spatial study at 4 nm-thick CTL by varying the Ge-incorporated region within the CTL, examining both the tunneling oxide proximal (<inline-formula> <tex-math>$T_{mathrm {OX}}$ </tex-math></inline-formula>-proximal) Ge:SiN device and the blocking oxide proximal (<inline-formula> <tex-math>$B_{mathrm {OX}}$ </tex-math></inline-formula>-proximal) Ge:SiN device. The <inline-formula> <tex-math>$B_{mathrm {OX}}$ </tex-math></inline-formula>-proximal Ge:SiN device consistently exhibits memory performance enhancement. These results provide guidelines for the spatial engineering of Ge:SiN CTL, confirming that the memory performance advantages of the Ge incorporation persist down to 4 nm and supporting a <inline-formula> <tex-math>$B_{mathrm {OX}}$ </tex-math></inline-formula>-proximal Ge incorporation. The material and spatial engineering demonstrate the potential of Ge:SiN CTL for next generation 3D NAND flash memory.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"122-126"},"PeriodicalIF":2.4,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11373295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Suppressing dark noise in silicon photomultipliers (SiPMs) remains highly challenging because Geiger-mode operation inherently leads to high dark count rates (DCR). Although epitaxial silicon layers grown on heavily doped substrates are widely employed, high-temperature epitaxial processing often induces dopant autodoping and the formation of interface states, which significantly exacerbate noise. In this work, we demonstrate that SiPMs fabricated on antimony (Sb)-doped substrates exhibit approximately 20% lower DCR, up to 40% higher photon detection efficiency, and about 15% improvement in single-photon timing resolution at an excess bias of 8 V, compared with their arsenic (As)-doped counterparts. These performance enhancements are attributed to the larger covalent radius and higher diffusion activation energy of Sb, which effectively suppress autodoping and minimize interface-state formation at the epitaxial–substrate boundary, thereby enabling low-noise, high-precision SiPM operation.
{"title":"Sb-Doped Substrates for Low-Noise Silicon Photomultipliers","authors":"Shifeng Zhang;Jiangteng Xia;Yanling Ren;Fudexuan Huang;Jiacheng Lai;Ming Zhang;Anqi Hu;Xia Guo","doi":"10.1109/JEDS.2026.3661177","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3661177","url":null,"abstract":"Suppressing dark noise in silicon photomultipliers (SiPMs) remains highly challenging because Geiger-mode operation inherently leads to high dark count rates (DCR). Although epitaxial silicon layers grown on heavily doped substrates are widely employed, high-temperature epitaxial processing often induces dopant autodoping and the formation of interface states, which significantly exacerbate noise. In this work, we demonstrate that SiPMs fabricated on antimony (Sb)-doped substrates exhibit approximately 20% lower DCR, up to 40% higher photon detection efficiency, and about 15% improvement in single-photon timing resolution at an excess bias of 8 V, compared with their arsenic (As)-doped counterparts. These performance enhancements are attributed to the larger covalent radius and higher diffusion activation energy of Sb, which effectively suppress autodoping and minimize interface-state formation at the epitaxial–substrate boundary, thereby enabling low-noise, high-precision SiPM operation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"107-112"},"PeriodicalIF":2.4,"publicationDate":"2026-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11371612","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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