Pub Date : 2025-04-10DOI: 10.1109/JEDS.2025.3558645
{"title":"Call for Nominations for Editor-in-Chief IEEE Electron Device Letters","authors":"","doi":"10.1109/JEDS.2025.3558645","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3558645","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1076-1076"},"PeriodicalIF":2.0,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960702","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/JEDS.2025.3558646
{"title":"Call for Nominations for Editor-in-Chief IEEE Transactions on Electron Devices(TED)","authors":"","doi":"10.1109/JEDS.2025.3558646","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3558646","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1077-1077"},"PeriodicalIF":2.0,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10960700","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/JEDS.2025.3557401
Oliver Durnan;Reem Alshanbari;Hong-Rae Cho;Ioannis Kymissis;Chang-Hyun Kim
This paper investigates the dependence of effective carrier mobility on the channel length in oxide thin-film transistors (TFTs). Bottom-gate staggered TFTs fabricated with a sputtered indium-galliumzinc-oxide channel exhibit a substantial increase in field-effect mobility with decreasing channel length, which is at variance with typical manifestation of contact resistance. An original model is thus proposed to describe the channel-length-dependent mobility in these TFTs. By decoupling local and intrinsic transport properties affecting the drain current, the model reproduces and rationalizes the observed phenomena. These results provide both a practical modeling tool and fundamental insights into the behaviors of oxide TFTs associated with the charge injection at their metal/semiconductor interface.
{"title":"Modeling the Increase in Effective Mobility in Short-Channel Oxide Thin-Film Transistors","authors":"Oliver Durnan;Reem Alshanbari;Hong-Rae Cho;Ioannis Kymissis;Chang-Hyun Kim","doi":"10.1109/JEDS.2025.3557401","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3557401","url":null,"abstract":"This paper investigates the dependence of effective carrier mobility on the channel length in oxide thin-film transistors (TFTs). Bottom-gate staggered TFTs fabricated with a sputtered indium-galliumzinc-oxide channel exhibit a substantial increase in field-effect mobility with decreasing channel length, which is at variance with typical manifestation of contact resistance. An original model is thus proposed to describe the channel-length-dependent mobility in these TFTs. By decoupling local and intrinsic transport properties affecting the drain current, the model reproduces and rationalizes the observed phenomena. These results provide both a practical modeling tool and fundamental insights into the behaviors of oxide TFTs associated with the charge injection at their metal/semiconductor interface.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"350-354"},"PeriodicalIF":2.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10948409","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we propose a p-NiO/n-Ga2O3 hetero-junction (HJ) Schottky barrier diode (SBD) with low turn-on voltage (Von) and high breakdown voltage (BV) with a trench SBD as a control. An investigation of its electrical characteristics is simulated by Sentaurus TCAD. The HJ SBD utilizes a low work-function anode metal to form a top electrode by reducing the $rm V_{on}$ of the diode at the forward state. A fin structure and metal/semiconductor (M/S) junction or PN HJ was employed to achieve an enhanced BV at the reverse state. An attempt to optimize the electrical characteristics of the device by modifying its structural parameters is also comprehensively analyzed in this work. The HJ SBD achieves a low $rm V_{on}$ of 0.57 V and a Power Figure of Merit (P-FOM) of 3.79 GW/cm2, simultaneously. The proposed structure provides a new approach for realizing high performance $beta $ -Ga2O3 SBDs with high reverse blocking and low loss capabilities.
{"title":"Proposal and Simulation of β-Ga₂O₃ Hetero- Junction Schottky Diodes With Low Work-Function Anode and High Breakdown Voltage","authors":"Ce Wang;Hong Zhou;Sami Alghamdi;Chunxu Su;Zhihong Liu;Kui Dang;Xuefeng Zheng;Xiaohua Ma;Peijun Ma;Yue Hao;Jincheng Zhang","doi":"10.1109/JEDS.2025.3556408","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556408","url":null,"abstract":"In this work, we propose a p-NiO/n-Ga2O3 hetero-junction (HJ) Schottky barrier diode (SBD) with low turn-on voltage (Von) and high breakdown voltage (BV) with a trench SBD as a control. An investigation of its electrical characteristics is simulated by Sentaurus TCAD. The HJ SBD utilizes a low work-function anode metal to form a top electrode by reducing the <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of the diode at the forward state. A fin structure and metal/semiconductor (M/S) junction or PN HJ was employed to achieve an enhanced BV at the reverse state. An attempt to optimize the electrical characteristics of the device by modifying its structural parameters is also comprehensively analyzed in this work. The HJ SBD achieves a low <inline-formula> <tex-math>$rm V_{on}$ </tex-math></inline-formula> of 0.57 V and a Power Figure of Merit (P-FOM) of 3.79 GW/cm2, simultaneously. The proposed structure provides a new approach for realizing high performance <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 SBDs with high reverse blocking and low loss capabilities.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"334-342"},"PeriodicalIF":2.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945755","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1109/JEDS.2025.3552036
Pragya R. Shrestha;Alexander Zaslavsky;Valery Ortiz Jimenez;Jason P. Campbell;Curt A. Richter
This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of ($10{^{{7}}}~I_{1}$ /$I_{0}$ sense current ratio) and prolonged retention. The memory is enabled by the bistable $I_{D}$ –$V_{G}$ transistor characteristics due to impact ionization (II) at cryogenic temperatures (T < 30 K). Focusing on critical memory reliability parameters—switching time, endurance, and retention characteristics—we present write/erase speeds down to $approx ~45$ ns at T < 10 K and cycling endurance surpassing $10^{9}$ cycles while maintaining the $I_{1}$ /$I_{0}$ memory window. Retention times of >10 s with a 30x memory window were observed in extensive high-speed measurements. The fast switching and retention characteristics combine to yield a low power ($mu $ W-range) candidate for local cache memory to support quantum sensing or quantum computing control circuitry. Additionally, our study outlines essential measurements crucial for exploring the viability of alternative memory solutions for low-temperature quantum sensing and computation applications.
{"title":"Impact-Ionization-Based High-Endurance One-Transistor Bulk CMOS Cryogenic Memory","authors":"Pragya R. Shrestha;Alexander Zaslavsky;Valery Ortiz Jimenez;Jason P. Campbell;Curt A. Richter","doi":"10.1109/JEDS.2025.3552036","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552036","url":null,"abstract":"This paper presents a high-endurance capacitorless one-transistor (1T) cryogenic memory, fabricated in a 180 nm bulk CMOS technology, with a high memory window of (<inline-formula> <tex-math>$10{^{{7}}}~I_{1}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{0}$ </tex-math></inline-formula> sense current ratio) and prolonged retention. The memory is enabled by the bistable <inline-formula> <tex-math>$I_{D}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V_{G}$ </tex-math></inline-formula> transistor characteristics due to impact ionization (II) at cryogenic temperatures (T < 30 K). Focusing on critical memory reliability parameters—switching time, endurance, and retention characteristics—we present write/erase speeds down to <inline-formula> <tex-math>$approx ~45$ </tex-math></inline-formula> ns at T < 10 K and cycling endurance surpassing <inline-formula> <tex-math>$10^{9}$ </tex-math></inline-formula> cycles while maintaining the <inline-formula> <tex-math>$I_{1}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{0}$ </tex-math></inline-formula> memory window. Retention times of >10 s with a 30x memory window were observed in extensive high-speed measurements. The fast switching and retention characteristics combine to yield a low power (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W-range) candidate for local cache memory to support quantum sensing or quantum computing control circuitry. Additionally, our study outlines essential measurements crucial for exploring the viability of alternative memory solutions for low-temperature quantum sensing and computation applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"355-361"},"PeriodicalIF":2.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10946245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1109/JEDS.2025.3556316
Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu
This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage ($leq 0.5$ V) and high on/off ratio $geq 10{^{{5}}}$ . Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L$leq 0.6mu $ m and A$leq 0.3mu $ m2). Smaller flake contact perimeters $leq 1.2mu $ m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles $leq 65{^{text {o}}}$ likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.
{"title":"Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors","authors":"Maria Vitoria Guimaraes Leal;Ahmad Azizimanesh;Nazmul Hasan;Stephen M. Wu","doi":"10.1109/JEDS.2025.3556316","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3556316","url":null,"abstract":"This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T’) and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage (<inline-formula> <tex-math>$leq 0.5$ </tex-math></inline-formula>V) and high on/off ratio <inline-formula> <tex-math>$geq 10{^{{5}}}$ </tex-math></inline-formula>. Small length and area of the contact between the metal stressor and the 2D 1T’-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L<inline-formula> <tex-math>$leq 0.6mu $ </tex-math></inline-formula>m and A<inline-formula> <tex-math>$leq 0.3mu $ </tex-math></inline-formula>m2). Smaller flake contact perimeters <inline-formula> <tex-math>$leq 1.2mu $ </tex-math></inline-formula>m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles <inline-formula> <tex-math>$leq 65{^{text {o}}}$ </tex-math></inline-formula> likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"343-349"},"PeriodicalIF":2.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945750","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fin Field-Effect-Transistor (FinFET) has become fundamental components in advanced integrated circuit, while the drain-extended FinFET (DE-FinFET) features a lightly doped drain extension region to improve the device’s breakdown voltage. However, both structural refinement and the optimal integration of various parameters remain limited in achieving comprehensive optimization of device performance. This study introduces a novel DE-FinFET featuring a stepped field plate to improve overall performance of device. Moreover, within an AI-assisted design framework, predictive modeling and multi-objective optimization of the device are accomplished using Kolmogorov–Arnold Networks (KAN) and the Nondominated Sorting Genetic Algorithm (NSGA-III). More importantly, the proposed framework enables efficient device design and performance evaluation, achieving an average prediction accuracy of 98.19% for electrical performance metrics while being over two million times faster than traditional Technology Computer-Aided-Design (TCAD) simulations. In addition, it effectively generates Pareto-optimal solutions, delivering an average improvement of 9.03% across key electrical performance metrics. The proposed novel device of DE-FinFET offers a new route toward tailoring electrical properties. Meanwhile, the methodology of AI-assisted design not only accelerates device design but also enables customizable solutions for multi-purpose applications.
{"title":"AI-Assisted Design of Drain-Extended FinFET With Stepped Field Plate for Multi-Purpose Applications","authors":"Xiaoyun Huang;Hongyu Tang;Chenggang Xu;Yuxuan Zhu;Yan Pan;Dawei Gao;Yitao Ma;Kai Xu","doi":"10.1109/JEDS.2025.3555327","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3555327","url":null,"abstract":"Fin Field-Effect-Transistor (FinFET) has become fundamental components in advanced integrated circuit, while the drain-extended FinFET (DE-FinFET) features a lightly doped drain extension region to improve the device’s breakdown voltage. However, both structural refinement and the optimal integration of various parameters remain limited in achieving comprehensive optimization of device performance. This study introduces a novel DE-FinFET featuring a stepped field plate to improve overall performance of device. Moreover, within an AI-assisted design framework, predictive modeling and multi-objective optimization of the device are accomplished using Kolmogorov–Arnold Networks (KAN) and the Nondominated Sorting Genetic Algorithm (NSGA-III). More importantly, the proposed framework enables efficient device design and performance evaluation, achieving an average prediction accuracy of 98.19% for electrical performance metrics while being over two million times faster than traditional Technology Computer-Aided-Design (TCAD) simulations. In addition, it effectively generates Pareto-optimal solutions, delivering an average improvement of 9.03% across key electrical performance metrics. The proposed novel device of DE-FinFET offers a new route toward tailoring electrical properties. Meanwhile, the methodology of AI-assisted design not only accelerates device design but also enables customizable solutions for multi-purpose applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"326-333"},"PeriodicalIF":2.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10943177","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-21DOI: 10.1109/JEDS.2025.3547035
Anne S. Verhulst
{"title":"Editorial for the J-EDS Special Issue for ESSERC 2024","authors":"Anne S. Verhulst","doi":"10.1109/JEDS.2025.3547035","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3547035","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"189-189"},"PeriodicalIF":2.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10936519","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-21DOI: 10.1109/JEDS.2025.3553583
Antonio Vettoliere;Fabio Chiarella;Vincenzo Izzo;Marcello Campajola;Paolo Scotto Di Vettimo;Patrizia Minutolo;Alberto Aloisio;Ettore Sarnelli
We analyzed the dynamic response to the light of organic field-effect transistors in bottom-gate/top-contact configuration. We fabricated Al/Al2O3/SAM/DNTT/Au phototransistors by evaporating thin film layers through shadow masks on flexible PEN (polyethylene naphthalate) substrates. The structure is composed of Al layer as the gate electrode, and Au used both for Source and Drain electrodes. DNTT (Dinaphtho[2,3-b:$2^{prime }$ ,$3^{prime }$ -f]thieno[3,2-b]thiophene) is the active organic semiconductor layer and Al2O3 is the dielectric material, chosen for the high value of the dielectric constant. SAM (self-assembled monolayer) was used to improve adhesion and interface properties between Al2O3 and DNTT. The transistors, sensitive to blue light, were biased at low-voltage (Vgs and $mathrm { V_{ds}}$ from 0 to 3.5 V). Devices showed low $mathrm { I_{gs}}$ leakage currents, of the order of $5x10^{-10}$ A, and a clear electro-optical response to the light. The maximum responsivity value was about 0.21 A/W in the static regime, while the lowest irradiance producing a measurable response in dynamic regime was $13~mu $ W/cm2. Fast time components of the rise time of the light response for the analyzed phototransistors, of the order of few hundreds of ms, turned out to be among the fastest reported in literature for Al/AlOx/DNTT/Au organic phototransistor. These preliminary results are encouraging for developing organic phototransistors for visible light communication.
{"title":"Dynamic Response of Low-Voltage Thin Film Phototransistors Based on DNTT Organic Semiconductor","authors":"Antonio Vettoliere;Fabio Chiarella;Vincenzo Izzo;Marcello Campajola;Paolo Scotto Di Vettimo;Patrizia Minutolo;Alberto Aloisio;Ettore Sarnelli","doi":"10.1109/JEDS.2025.3553583","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3553583","url":null,"abstract":"We analyzed the dynamic response to the light of organic field-effect transistors in bottom-gate/top-contact configuration. We fabricated Al/Al2O3/SAM/DNTT/Au phototransistors by evaporating thin film layers through shadow masks on flexible PEN (polyethylene naphthalate) substrates. The structure is composed of Al layer as the gate electrode, and Au used both for Source and Drain electrodes. DNTT (Dinaphtho[2,3-b:<inline-formula> <tex-math>$2^{prime }$ </tex-math></inline-formula>,<inline-formula> <tex-math>$3^{prime }$ </tex-math></inline-formula>-f]thieno[3,2-b]thiophene) is the active organic semiconductor layer and Al2O3 is the dielectric material, chosen for the high value of the dielectric constant. SAM (self-assembled monolayer) was used to improve adhesion and interface properties between Al2O3 and DNTT. The transistors, sensitive to blue light, were biased at low-voltage (Vgs and <inline-formula> <tex-math>$mathrm { V_{ds}}$ </tex-math></inline-formula> from 0 to 3.5 V). Devices showed low <inline-formula> <tex-math>$mathrm { I_{gs}}$ </tex-math></inline-formula> leakage currents, of the order of <inline-formula> <tex-math>$5x10^{-10}$ </tex-math></inline-formula> A, and a clear electro-optical response to the light. The maximum responsivity value was about 0.21 A/W in the static regime, while the lowest irradiance producing a measurable response in dynamic regime was <inline-formula> <tex-math>$13~mu $ </tex-math></inline-formula>W/cm2. Fast time components of the rise time of the light response for the analyzed phototransistors, of the order of few hundreds of ms, turned out to be among the fastest reported in literature for Al/AlOx/DNTT/Au organic phototransistor. These preliminary results are encouraging for developing organic phototransistors for visible light communication.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"317-325"},"PeriodicalIF":2.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10937183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/JEDS.2025.3552171
Woo Jin Baek;Joon Pyo Kim;Song Hyeon Kuk;Juhyuk Park;Hyun Soo Kim;Dae-Myeong Geum;Sang Hyeon Kim
We demonstrate field-effect passivation (FEP) of GaN-based blue $mu $ LEDs by incorporating an additional metal-oxide-semiconductor gate structure on the sidewalls. This approach allows for active control of surface band bending at the sidewalls, thereby modulating carrier trapping and de-trapping. We observe that applying a negative gate voltage $(V_{G})$ facilitates electron de-trapping, leading to a reduction in surface recombination and a corresponding decrease in current, as evidenced by an enhanced external quantum efficiency (EQE). Conversely, applying a positive $V_{G}$ results in the opposite effect.
{"title":"Field-Effect Passivation of GaN-Based Blue Micro-Light-Emitting Diodes","authors":"Woo Jin Baek;Joon Pyo Kim;Song Hyeon Kuk;Juhyuk Park;Hyun Soo Kim;Dae-Myeong Geum;Sang Hyeon Kim","doi":"10.1109/JEDS.2025.3552171","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3552171","url":null,"abstract":"We demonstrate field-effect passivation (FEP) of GaN-based blue <inline-formula> <tex-math>$mu $ </tex-math></inline-formula> LEDs by incorporating an additional metal-oxide-semiconductor gate structure on the sidewalls. This approach allows for active control of surface band bending at the sidewalls, thereby modulating carrier trapping and de-trapping. We observe that applying a negative gate voltage <inline-formula> <tex-math>$(V_{G})$ </tex-math></inline-formula> facilitates electron de-trapping, leading to a reduction in surface recombination and a corresponding decrease in current, as evidenced by an enhanced external quantum efficiency (EQE). Conversely, applying a positive <inline-formula> <tex-math>$V_{G}$ </tex-math></inline-formula> results in the opposite effect.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"303-307"},"PeriodicalIF":2.0,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930472","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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