Pub Date : 2024-10-28DOI: 10.1109/JEDS.2024.3486454
Pingyu Cao;Kepeng Zhao;Harm Van Zalinge;Ping Zhang;Miao Cui;Fei Xue
This paper presents a high gain voltage amplifier based on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with monolithically integrated enhancement-mode (E-mode) and depletion-mode (D-mode) devices. The GaN amplifier consists of differential pair based on E-mode devices, active loads based on D-mode devices and a current source, and the influence of the current source on voltage gain was evaluated. The proposed amplifier demonstrates a high gain and high unity-gain frequency at both room temperature (25 °C) and high-temperature (250 °C). The gain is 37.4 dB at room temperature, slightly decreasing to 32.7 dB when the temperature rises to 250 °C. Moreover, the power consumption reported in this work is decreased to 60 mW by reducing the static current, and the chip area of this work is reduced to $2.806{times 10^{5}mu {mathrm { m^{2}}}}$ . These results indicate that the proposed amplifier is suitable for small signal sensing or driving circuits, which would promise high power density for GaN-on-Si integration circuits with high-temperature operation.
本文介绍了一种基于氮化镓/氮化镓金属绝缘体-半导体高电子迁移率晶体管（MIS-HEMT）的高增益电压放大器，该放大器具有单片集成的增强型（E 模）和耗尽型（D 模）器件。GaN 放大器由基于 E 模式器件的差分对、基于 D 模式器件的有源负载和电流源组成，并评估了电流源对电压增益的影响。所提出的放大器在室温（25 °C）和高温（250 °C）条件下均表现出较高的增益和较高的单位增益频率。室温下的增益为 37.4 dB，当温度升至 250 °C 时，增益略降至 32.7 dB。此外，通过减小静态电流，本作品中报告的功耗降低到 60 mW，芯片面积减小到 2.806{times 10^{5}mu {mathrm { m^{2}}}}$ 。这些结果表明，所提出的放大器适用于小信号传感或驱动电路，有望为高温工作的硅基氮化镓集成电路带来高功率密度。
{"title":"AlGaN/GaN High Electron Mobility Transistor Amplifier for High-Temperature Operation","authors":"Pingyu Cao;Kepeng Zhao;Harm Van Zalinge;Ping Zhang;Miao Cui;Fei Xue","doi":"10.1109/JEDS.2024.3486454","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3486454","url":null,"abstract":"This paper presents a high gain voltage amplifier based on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with monolithically integrated enhancement-mode (E-mode) and depletion-mode (D-mode) devices. The GaN amplifier consists of differential pair based on E-mode devices, active loads based on D-mode devices and a current source, and the influence of the current source on voltage gain was evaluated. The proposed amplifier demonstrates a high gain and high unity-gain frequency at both room temperature (25 °C) and high-temperature (250 °C). The gain is 37.4 dB at room temperature, slightly decreasing to 32.7 dB when the temperature rises to 250 °C. Moreover, the power consumption reported in this work is decreased to 60 mW by reducing the static current, and the chip area of this work is reduced to \u0000<inline-formula> <tex-math>$2.806{times 10^{5}mu {mathrm { m^{2}}}}$ </tex-math></inline-formula>\u0000. These results indicate that the proposed amplifier is suitable for small signal sensing or driving circuits, which would promise high power density for GaN-on-Si integration circuits with high-temperature operation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10737042","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-28DOI: 10.1109/JEDS.2024.3486736
Xuejing Yang;Kyounghoon Yang
In this paper, we report on newly introduced direct extraction methods applied for determining the extrinsic parasitic capacitances and inductances in RF test structures of Fully-Depleted-Silicon-On-Insulator (FDSOI) MOSFETs with a 28 nm gate length. Our approach leverages dummy structures and employs closed-form extraction techniques for precise parasitic parameter determination. Notably, we apply the closed-form extraction strategy for the first time to quantify the parasitic inductances of RF FDSOI-MOSFETs. To verify the accuracy of our extraction results based on a direct approach without optimization, we perform error analysis by comparing the modeled S-parameters of the small signal equivalent circuit to the measured results. Good agreement between the modeled and measured results not only at the cold bias but also at the saturation-mode operation region is achieved up to 110 GHz.
{"title":"Direct Extraction Methods for RF Characterization of Extrinsic Parasitic Parameters in 28 nm FDSOI MOSFETs Up to 110 GHz","authors":"Xuejing Yang;Kyounghoon Yang","doi":"10.1109/JEDS.2024.3486736","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3486736","url":null,"abstract":"In this paper, we report on newly introduced direct extraction methods applied for determining the extrinsic parasitic capacitances and inductances in RF test structures of Fully-Depleted-Silicon-On-Insulator (FDSOI) MOSFETs with a 28 nm gate length. Our approach leverages dummy structures and employs closed-form extraction techniques for precise parasitic parameter determination. Notably, we apply the closed-form extraction strategy for the first time to quantify the parasitic inductances of RF FDSOI-MOSFETs. To verify the accuracy of our extraction results based on a direct approach without optimization, we perform error analysis by comparing the modeled S-parameters of the small signal equivalent circuit to the measured results. Good agreement between the modeled and measured results not only at the cold bias but also at the saturation-mode operation region is achieved up to 110 GHz.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736559","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FeFETs have significant potential for use in non-volatile memory applications. This is primarily due to their compatibility with CMOS technology and reliable switching characteristics. Previous studies have primarily concentrated on the endurance and memory window properties, while this study focuses on the short-term (< $1~mu $ s) retention region of MFMIS FeFETs. Specifically, we examine the impact of the capacitance ratio of the ferroelectric capacitor (CFE) and the MOS capacitor (CDE) on short-term retention. Additionally, we conducted simulations to validate the experimental observations and investigate the interaction of the depolarization field with the charge trapping and polarization of the MFMIS structure. This study emphasizes the crucial role of controlling the CDE: ${mathrm { C}}_{mathrm { FE}}$ ratio in enhancing the short-term retention of MFMIS FeFETs. Its findings enhance our understanding of short-term retention mechanisms and provide a pathway for improving performance and functionality in non-volatile memory technology design.
{"title":"The Effect of Ferroelectric/Dielectric Capacitance Ratio on Short-Term Retention Characteristics of MFMIS FeFET","authors":"Junghyeon Hwang;Giuk Kim;Hongrae Joh;Jinho Ahn;Sanghun Jeon","doi":"10.1109/JEDS.2024.3485869","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3485869","url":null,"abstract":"Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FeFETs have significant potential for use in non-volatile memory applications. This is primarily due to their compatibility with CMOS technology and reliable switching characteristics. Previous studies have primarily concentrated on the endurance and memory window properties, while this study focuses on the short-term (<\u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000s) retention region of MFMIS FeFETs. Specifically, we examine the impact of the capacitance ratio of the ferroelectric capacitor (CFE) and the MOS capacitor (CDE) on short-term retention. Additionally, we conducted simulations to validate the experimental observations and investigate the interaction of the depolarization field with the charge trapping and polarization of the MFMIS structure. This study emphasizes the crucial role of controlling the CDE: \u0000<inline-formula> <tex-math>${mathrm { C}}_{mathrm { FE}}$ </tex-math></inline-formula>\u0000 ratio in enhancing the short-term retention of MFMIS FeFETs. Its findings enhance our understanding of short-term retention mechanisms and provide a pathway for improving performance and functionality in non-volatile memory technology design.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10734331","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-18DOI: 10.1109/JEDS.2024.3483299
Mohammad Bavir;Abdollah Abbasi;Ali Asghar Orouji;Farzan Jazaeri;Jean-Michel Sallese
In this paper an analytical non-quasi-static (NQS) model for long-channel symmetric double-gate junctionless field-effect transistors (JLFETs) operating in depletion mode is proposed for the first time. The model addresses the limitations of existing DC and AC models by incorporating time-dependent current continuity equations which are essentials to predict JLFETs behavior at high frequencies. Leveraging charge-based equations, the NQS model captures the delay between current and applied potentials arising beyond the quasi-static regime. Analytical solutions for small-signal perturbations allow the calculation of key transistor small signal parameters such as the gate transadmittance. The model’s validity is tested against TCAD simulations for various device parameters, including doping concentration and channel thickness. Good agreement between the model and TCAD simulations is observed across a wide frequency range, up to highly non-static transport conditions. This work lays the foundation for a comprehensive RF model of JLFETs for high-frequency applications.
{"title":"Non Quasi-Static Model of DG Junctionless FETs","authors":"Mohammad Bavir;Abdollah Abbasi;Ali Asghar Orouji;Farzan Jazaeri;Jean-Michel Sallese","doi":"10.1109/JEDS.2024.3483299","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3483299","url":null,"abstract":"In this paper an analytical non-quasi-static (NQS) model for long-channel symmetric double-gate junctionless field-effect transistors (JLFETs) operating in depletion mode is proposed for the first time. The model addresses the limitations of existing DC and AC models by incorporating time-dependent current continuity equations which are essentials to predict JLFETs behavior at high frequencies. Leveraging charge-based equations, the NQS model captures the delay between current and applied potentials arising beyond the quasi-static regime. Analytical solutions for small-signal perturbations allow the calculation of key transistor small signal parameters such as the gate transadmittance. The model’s validity is tested against TCAD simulations for various device parameters, including doping concentration and channel thickness. Good agreement between the model and TCAD simulations is observed across a wide frequency range, up to highly non-static transport conditions. This work lays the foundation for a comprehensive RF model of JLFETs for high-frequency applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10722036","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142587499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper demonstrated high-output-power and high-efficiency power amplifier (PA) monolithic microwave-integrated circuit (MMIC) at 300-GHz band (252–296 GHz) with the use of InPbased metal–oxide–semiconductor high-electron-mobility transistors (HEMTs) with composite-channel (CC) and double-side-doping (DD) techniques. The CC-DD structure obtained high output current and low channel resistance due to the improved carrier density and mobility. W-band load-pull measurement revealed the drastically improved output power density of CC-DD structure compared with that of singlechannel DD structure. The 2-stage cascaded, 4-way, and 16-way PA-MMICs were designed based on stacked common-gate transistors with current reuse topology. The cascaded PA-MMIC exhibited a poweradded efficiency (PAE) of 7.8%, and the 16-way PA-MMIC exhibited an output power of 16.9 dBm. These values are the highest among all the values reported for the 300-GHz band PA-MMICs. The 4-way PA-MMIC achieved a high output power of 13.6–14.6 dBm and high PAE of 4.8%–6.3% simultaneously at the entire 300-GHz band.
{"title":"High Output Power and Efficiency 300-GHz Band InP-Based MOS-HEMT Power Amplifiers With Composite-Channel and Double-Side Doping","authors":"Yusuke Kumazaki;Shiro Ozaki;Naoya Okamoto;Naoki Hara;Yasuhiro Nakasha;Masaru Sato;Toshihiro Ohki","doi":"10.1109/JEDS.2024.3483305","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3483305","url":null,"abstract":"This paper demonstrated high-output-power and high-efficiency power amplifier (PA) monolithic microwave-integrated circuit (MMIC) at 300-GHz band (252–296 GHz) with the use of InPbased metal–oxide–semiconductor high-electron-mobility transistors (HEMTs) with composite-channel (CC) and double-side-doping (DD) techniques. The CC-DD structure obtained high output current and low channel resistance due to the improved carrier density and mobility. W-band load-pull measurement revealed the drastically improved output power density of CC-DD structure compared with that of singlechannel DD structure. The 2-stage cascaded, 4-way, and 16-way PA-MMICs were designed based on stacked common-gate transistors with current reuse topology. The cascaded PA-MMIC exhibited a poweradded efficiency (PAE) of 7.8%, and the 16-way PA-MMIC exhibited an output power of 16.9 dBm. These values are the highest among all the values reported for the 300-GHz band PA-MMICs. The 4-way PA-MMIC achieved a high output power of 13.6–14.6 dBm and high PAE of 4.8%–6.3% simultaneously at the entire 300-GHz band.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10722855","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Metal Oxide Thin Film Transistors (MO TFTs) have garnered considerable interest in emerging Internet of Things (IoT) fields such as wearable electronics, displays, Radio Frequency Identification (RFID), and biomedical monitoring, owing to their flexibility and transparency. However, limitations in channel materials make MO TFT-based circuits unipolar. Unipolar circuits often exhibit elevated short-circuit power consumption, which restricts the development of MO TFTs in the IoT sector. This paper introduces a Capacitively Coupled Near-Threshold Biasing (CCNB) technique that leverages the unique Capacitance-Voltage (C-V) characteristics of MO TFTs to bias devices in the near-threshold region, achieving nearly a 95% reduction in power consumption compared to traditional designs with the device coupling ratio (channel capacitance/overlap capacitance) at 40. Furthermore, considering the significance of clock signals in IoT applications, we have also developed a low-power full-swing Ring Oscillator (RO) based on our CCNB technique, resulting in a 90% reduction in power consumption and a nearly 70% reduction in PDP compared to conventional low-power designs.
金属氧化物薄膜晶体管（MO TFT）因其灵活性和透明度，在可穿戴电子设备、显示器、射频识别（RFID）和生物医学监测等新兴物联网（IoT）领域备受关注。然而，由于沟道材料的限制，基于 MO TFT 的电路都是单极电路。单极电路通常表现出较高的短路功耗，这限制了 MO TFT 在物联网领域的发展。本文介绍了一种电容耦合近阈值偏置（CCNB）技术，该技术利用 MO TFT 独特的电容-电压（C-V）特性在近阈值区对器件进行偏置，与器件耦合比（沟道电容/重叠电容）为 40 的传统设计相比，功耗降低了近 95%。此外，考虑到时钟信号在物联网应用中的重要性，我们还开发了基于 CCNB 技术的低功耗全摆环振荡器 (RO)，与传统低功耗设计相比，功耗降低了 90%，PDP 降低了近 70%。
{"title":"Capacitively Coupled Near-Threshold Biasing: Low-Power Design Based on Metal Oxide TFTs for IoT Applications","authors":"Yixin Fu;Zhixuan Wang;Shuai Yuan;Shengdong Zhang;Yudi Zhao;Junchen Dong;Kai Zhao","doi":"10.1109/JEDS.2024.3480269","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3480269","url":null,"abstract":"Metal Oxide Thin Film Transistors (MO TFTs) have garnered considerable interest in emerging Internet of Things (IoT) fields such as wearable electronics, displays, Radio Frequency Identification (RFID), and biomedical monitoring, owing to their flexibility and transparency. However, limitations in channel materials make MO TFT-based circuits unipolar. Unipolar circuits often exhibit elevated short-circuit power consumption, which restricts the development of MO TFTs in the IoT sector. This paper introduces a Capacitively Coupled Near-Threshold Biasing (CCNB) technique that leverages the unique Capacitance-Voltage (C-V) characteristics of MO TFTs to bias devices in the near-threshold region, achieving nearly a 95% reduction in power consumption compared to traditional designs with the device coupling ratio (channel capacitance/overlap capacitance) at 40. Furthermore, considering the significance of clock signals in IoT applications, we have also developed a low-power full-swing Ring Oscillator (RO) based on our CCNB technique, resulting in a 90% reduction in power consumption and a nearly 70% reduction in PDP compared to conventional low-power designs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10716537","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The kink effect of gate-all-around (GAA) MOSFET has been experimentally validated by our GAA devices fabricated on a void embedded silicon-on-insulator (VESOI) substrate. In this VESOI GAA device, a consistent and favorable decrease in subthreshold swing (SS) is observed as $V_{mathrm { d}}$ increases, which has rarely been reported in devices with other gate structures. In particular, the SS of the device reaches the minimum ~0.1mV/dec with no discernable hysteresis window at $V_{mathrm { d}} {=} 4.5$ V under ambient condition. Further device simulation strongly confirms the unique role of the GAA controllability over the hysteresis-free kink process. These findings contribute to a better understanding of kink behaviors within GAA device for potential application.
{"title":"Subthreshold Kink Effect in Gate-All-Around MOSFETs Based on Void Embedded Silicon on Insulator Technology","authors":"Yuxin Liu;Qiang Liu;Jin Chen;Zhiqiang Mu;Xing Wei;Wenjie Yu","doi":"10.1109/JEDS.2024.3478750","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3478750","url":null,"abstract":"The kink effect of gate-all-around (GAA) MOSFET has been experimentally validated by our GAA devices fabricated on a void embedded silicon-on-insulator (VESOI) substrate. In this VESOI GAA device, a consistent and favorable decrease in subthreshold swing (SS) is observed as \u0000<inline-formula> <tex-math>$V_{mathrm { d}}$ </tex-math></inline-formula>\u0000 increases, which has rarely been reported in devices with other gate structures. In particular, the SS of the device reaches the minimum ~0.1mV/dec with no discernable hysteresis window at \u0000<inline-formula> <tex-math>$V_{mathrm { d}} {=} 4.5$ </tex-math></inline-formula>\u0000V under ambient condition. Further device simulation strongly confirms the unique role of the GAA controllability over the hysteresis-free kink process. These findings contribute to a better understanding of kink behaviors within GAA device for potential application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10714381","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.
{"title":"Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs","authors":"Zhanhang Chen;Haoliang Shan;Ziyi Ding;Xia Wu;Xiaolin Cen;Xiaoyu Ma;Wanling Deng;Junkai Huang","doi":"10.1109/JEDS.2024.3477928","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3477928","url":null,"abstract":"A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10713252","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/JEDS.2024.3475289
Ao Zhang;Jianjun Gao
An improved EEHEMT nonlinear model with noise model has been developed in this paper. Empirical formulas of bias dependent noise model parameters are given. A four-stage 120–160 GHz monolithic low-noise amplifier (LNA) fabricated with the 70nm InAlAs/InGaAs/InP HEMT technology. The simulated results of S-parameters and noise figure show the good agreement with measured data to verify the accuracy of the proposed model.
{"title":"HEMT Noise Modeling for D Band Low Noise Amplifier Design","authors":"Ao Zhang;Jianjun Gao","doi":"10.1109/JEDS.2024.3475289","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3475289","url":null,"abstract":"An improved EEHEMT nonlinear model with noise model has been developed in this paper. Empirical formulas of bias dependent noise model parameters are given. A four-stage 120–160 GHz monolithic low-noise amplifier (LNA) fabricated with the 70nm InAlAs/InGaAs/InP HEMT technology. The simulated results of S-parameters and noise figure show the good agreement with measured data to verify the accuracy of the proposed model.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10706073","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-04DOI: 10.1109/JEDS.2024.3474291
Minxi Cai;Wei Zhong;Bei Liu;Piaorong Xu;Jing Cao
A DC model is proposed for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) applicable to various active layer thicknesses. With the back surface potential and its coupling with the front surface potential being considered, an explicit potential solution is developed. Then, the analytical drain current and physical definition of threshold voltage are derived based on a non-chargesheet expression of free charge density. It is verified that in the previous models for AOS TFTs, typically ignoring the back surface potential and the active layer thickness effects could result in obvious deviations in the values of parameters during the characterization of DC performance, especially for scaled devices with low channel thicknesses. By comparing with numerical calculations and experimental data, this model is validated to be more suitable for AOS TFTs with decreased dimensions, which could give more realistic distributions of the density of states in the channel during parameter extraction.
本文提出了适用于各种有源层厚度的非晶氧化物半导体（AOS）薄膜晶体管（TFT）的直流模型。考虑到后表面电势及其与前表面电势的耦合，建立了一个显式电势解决方案。然后，根据自由电荷密度的非电荷片表达式推导出分析漏极电流和阈值电压的物理定义。结果证明，在以往的 AOS TFT 模型中，通常忽略背面电势和有源层厚度效应会导致直流性能表征过程中的参数值出现明显偏差，特别是对于沟道厚度较低的缩放器件。通过与数值计算和实验数据的比较，验证了该模型更适用于尺寸减小的 AOS TFT，在参数提取过程中能给出更真实的沟道内态密度分布。
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