{"title":"Corrections to “Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure”","authors":"Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka","doi":"10.1109/JEDS.2025.3542189","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542189","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"134-134"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10913980","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A highly robust integrated gate driver based on organic thin-film transistors (OTFTs) is proposed that effectively addresses the output degradation caused by depletion-mode operation, instability and variation. The series-connected two-transistor structures and the inverters generate positive gateto- source voltages for internal nodes, which eliminate the leakage current and voltage ripples in depletion-mode operation and extend the support threshold voltage ($V_{TH}$ ) range. The simulation waveforms of the 538th stage have no degradation, considering the $Delta V_{TH}$ range from 1.18 to -0.53 V for single-gate (SG) OTFT and that from 2.13 to -8.07 V for dual-gate (DG) OTFT. The fabricated gate drivers generate stable scan signals with almost negligible voltage ripples for SG- and DG-OTFT with $V_{TH}$ of +7.9 and +1.8 V, respectively. In a 5.8-inch AMOLED panel (resolution: 538×302), the circuit can operate at a frame rate range from 1 to 45 Hz, driven by clocks with a frequency of 12.5 kHz and a swing from 0 to -15 V.
{"title":"A Highly Robust Integrated Gate Driver Based on Organic TFTs for Active-Matrix Displays","authors":"Wanming Wu;Chuanke Chen;Chunyu Zhang;Chen Gu;Yinzhi Tang;Shipeng Wang;Mengwen Yan;Qingding Tong;Di Geng;Ling Li","doi":"10.1109/JEDS.2025.3542951","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542951","url":null,"abstract":"A highly robust integrated gate driver based on organic thin-film transistors (OTFTs) is proposed that effectively addresses the output degradation caused by depletion-mode operation, instability and variation. The series-connected two-transistor structures and the inverters generate positive gateto- source voltages for internal nodes, which eliminate the leakage current and voltage ripples in depletion-mode operation and extend the support threshold voltage (<inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula>) range. The simulation waveforms of the 538th stage have no degradation, considering the <inline-formula> <tex-math>$Delta V_{TH}$ </tex-math></inline-formula> range from 1.18 to -0.53 V for single-gate (SG) OTFT and that from 2.13 to -8.07 V for dual-gate (DG) OTFT. The fabricated gate drivers generate stable scan signals with almost negligible voltage ripples for SG- and DG-OTFT with <inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula> of +7.9 and +1.8 V, respectively. In a 5.8-inch AMOLED panel (resolution: 538×302), the circuit can operate at a frame rate range from 1 to 45 Hz, driven by clocks with a frequency of 12.5 kHz and a swing from 0 to -15 V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"128-133"},"PeriodicalIF":2.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891473","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A self-aligned (SA) staggered structure for amorphous-In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is proposed. The bottom contact between n+-IGZO and source/drain (S/D) enables larger contact area and shorter current-transmission distance, thus reducing the contact resistance. The non-overlap structure helps to eliminate the overlap-induced parasitic capacitance, thereby improving the device operating speed. The fabricated SA staggered a-IGZO TFTs exhibit good performance, including channel-width-normalized contact resistance (RCW) as low as 1.53 $Omega cdot mathrm{~cm}$ and transit frequency (fT) as high as 1.4 GHz, which are quite competitive in the field of high-speed a-IGZO TFTs.
{"title":"Self-Aligned Staggered Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors With Ultra-Low Contact Resistance for High-Speed Circuits Application","authors":"Chuanke Chen;Xinlv Duan;Congyan Lu;Xichen Chuai;Wanming Wu;Chunyu Zhang;Chen Gu;Guanhua Yang;Nianduan Lu;Di Geng;Ling Li","doi":"10.1109/JEDS.2025.3543212","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3543212","url":null,"abstract":"A self-aligned (SA) staggered structure for amorphous-In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is proposed. The bottom contact between n+-IGZO and source/drain (S/D) enables larger contact area and shorter current-transmission distance, thus reducing the contact resistance. The non-overlap structure helps to eliminate the overlap-induced parasitic capacitance, thereby improving the device operating speed. The fabricated SA staggered a-IGZO TFTs exhibit good performance, including channel-width-normalized contact resistance (RCW) as low as 1.53 <inline-formula> <tex-math>$Omega cdot mathrm{~cm}$ </tex-math></inline-formula> and transit frequency (fT) as high as 1.4 GHz, which are quite competitive in the field of high-speed a-IGZO TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"135-138"},"PeriodicalIF":2.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891703","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper outlines the establishment of a generic cryogenic CMOS database in which key electrical parameters and transfer characteristics of the MOSFETs are quantified as functions of device size, temperature/frequency responses. Meanwhile, comprehensive device statistical analysis is conducted to evaluate the influence of variation and mismatch effects at low temperatures. Furthermore, by incorporating the Cryo-CMOS compact model into the process design kit (PDK), the cryogenic 4 Kb SRAM and 5-bit flash ADC are designed, and their performance is investigated and optimized based on the EDA-compatible platform, hence laying a solid foundation for large-scale cryogenic IC design.
{"title":"Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform for Reliable Cryogenic IC Design","authors":"Zhidong Tang;Zewei Wang;Yumeng Yuan;Chang He;Xin Luo;Ao Guo;Renhe Chen;Yongqi Hu;Longfei Yang;Chengwei Cao;Lin Lin Liu;Liujiang Yu;Ganbing Shang;Yongfeng Cao;Shoumian Chen;Yuhang Zhao;Shaojian Hu;Xufeng Kou","doi":"10.1109/JEDS.2025.3542589","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3542589","url":null,"abstract":"This paper outlines the establishment of a generic cryogenic CMOS database in which key electrical parameters and transfer characteristics of the MOSFETs are quantified as functions of device size, temperature/frequency responses. Meanwhile, comprehensive device statistical analysis is conducted to evaluate the influence of variation and mismatch effects at low temperatures. Furthermore, by incorporating the Cryo-CMOS compact model into the process design kit (PDK), the cryogenic 4 Kb SRAM and 5-bit flash ADC are designed, and their performance is investigated and optimized based on the EDA-compatible platform, hence laying a solid foundation for large-scale cryogenic IC design.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"117-127"},"PeriodicalIF":2.0,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) are fabricated on Si substrates with an ultra-high breakdown voltage of over 3 kV using a 90-nm in situ $textrm {SiN}_{mathrm { X}}$ layer as both the gate dielectric and surface passivation. The devices exhibit low off-state leakage current (on/off ratio of $10{^{{9}}}$ ), high forward gate breakdown voltage (>122 V), and state-of-the-art figure of merit (685 MW/cm2). Moreover, the reliability of the in situ $textrm {SiN}_{mathrm { X}}$ dielectric is evaluated through the high-temperature gate bias test. The results are fitted with a Weibull distribution, estimating a 10-year estimation of 100 ppm. The maximum gate-source voltage of over 70 V is obtained. This letter presents a strategy for mass producing GaN-on-Si MISHEMTs with high breakdown voltage and reliability.
{"title":"A 3-kV GaN MISHEMT With High Reliability and a Power Figure-of-Merit of 685 MW/cm²","authors":"Yifan Cui;Minghao He;Jianguo Chen;Yang Jiang;Chuying Tang;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2025.3533920","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3533920","url":null,"abstract":"In this letter, GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) are fabricated on Si substrates with an ultra-high breakdown voltage of over 3 kV using a 90-nm in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> layer as both the gate dielectric and surface passivation. The devices exhibit low off-state leakage current (on/off ratio of <inline-formula> <tex-math>$10{^{{9}}}$ </tex-math></inline-formula>), high forward gate breakdown voltage (>122 V), and state-of-the-art figure of merit (685 MW/cm2). Moreover, the reliability of the in situ <inline-formula> <tex-math>$textrm {SiN}_{mathrm { X}}$ </tex-math></inline-formula> dielectric is evaluated through the high-temperature gate bias test. The results are fitted with a Weibull distribution, estimating a 10-year estimation of 100 ppm. The maximum gate-source voltage of over 70 V is obtained. This letter presents a strategy for mass producing GaN-on-Si MISHEMTs with high breakdown voltage and reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"106-111"},"PeriodicalIF":2.0,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10886964","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-07DOI: 10.1109/JEDS.2025.3538769
Minghao He;Mujun Li;Chenkai Deng;Xiaohui Wang;Qing Wang;Hongyu Yu;Kah-Wee Ang
A charge trapping layer (CTL) technique is incorporated to achieve a normally-off Ga2O3 MOSFET. The gate dielectric was engineered using a stack composed of a blocking layer (16 nm ${mathrm { HfO}}_{mathrm { x}}$ / 2 nm Al2O3), a CTL (5.76 nm Al:HfO${_{text {x}}}~1$ :5), and a tunneling barrier (2 nm Al2O3 / 2 nm ${mathrm { HfO}}_{mathrm { x}}$ / 2 nm Al2O3). The trap profile of the CTL layer and the interface of the gate dielectric and Ga2O3 channel are studied by photon-stimulated characterization, which yield highly uniform results, indicating the high quality and uniformity of the proposed method. Furthermore, we conducted a time-dependent dielectric breakdown (TDDB) test on devices both without a field plate (NOFP) and with a source-connected field plate (SFP) to investigate the dielectric failure mechanism and gain valuable insights for the design of CTL-based Ga2O3 MOSFETs.
{"title":"Trap Analysis of Normally-Off Ga₂O₃ MOSFET Enabled by Charge Trapping Layer: Photon Stimulated Characterization and TDDB","authors":"Minghao He;Mujun Li;Chenkai Deng;Xiaohui Wang;Qing Wang;Hongyu Yu;Kah-Wee Ang","doi":"10.1109/JEDS.2025.3538769","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3538769","url":null,"abstract":"A charge trapping layer (CTL) technique is incorporated to achieve a normally-off Ga2O3 MOSFET. The gate dielectric was engineered using a stack composed of a blocking layer (16 nm <inline-formula> <tex-math>${mathrm { HfO}}_{mathrm { x}}$ </tex-math></inline-formula> / 2 nm Al2O3), a CTL (5.76 nm Al:HfO<inline-formula> <tex-math>${_{text {x}}}~1$ </tex-math></inline-formula>:5), and a tunneling barrier (2 nm Al2O3 / 2 nm <inline-formula> <tex-math>${mathrm { HfO}}_{mathrm { x}}$ </tex-math></inline-formula> / 2 nm Al2O3). The trap profile of the CTL layer and the interface of the gate dielectric and Ga2O3 channel are studied by photon-stimulated characterization, which yield highly uniform results, indicating the high quality and uniformity of the proposed method. Furthermore, we conducted a time-dependent dielectric breakdown (TDDB) test on devices both without a field plate (NOFP) and with a source-connected field plate (SFP) to investigate the dielectric failure mechanism and gain valuable insights for the design of CTL-based Ga2O3 MOSFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"112-116"},"PeriodicalIF":2.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10877719","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/JEDS.2025.3536136
{"title":"Call for Nominations for Editor-in-Chief","authors":"","doi":"10.1109/JEDS.2025.3536136","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3536136","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1075-1075"},"PeriodicalIF":2.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10858348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/JEDS.2025.3528210
{"title":"Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29","authors":"","doi":"10.1109/JEDS.2025.3528210","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3528210","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1074-1074"},"PeriodicalIF":2.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10858349","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/JEDS.2025.3536577
{"title":"2024 Index IEEE Journal of the Electron Devices Society Vol. 12","authors":"","doi":"10.1109/JEDS.2025.3536577","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3536577","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1070-1103"},"PeriodicalIF":2.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10858345","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143360897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/JEDS.2025.3528208
{"title":"Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/JEDS.2025.3528208","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3528208","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1070-1071"},"PeriodicalIF":2.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10858472","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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