Pub Date : 2026-01-28DOI: 10.1109/JEDS.2026.3659206
{"title":"2025 Index IEEE Journal of the Electron Devices Society Vol. 13","authors":"","doi":"10.1109/JEDS.2026.3659206","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3659206","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1337-1385"},"PeriodicalIF":2.4,"publicationDate":"2026-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11367240","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-22DOI: 10.1109/JEDS.2025.3650320
Tetsuo Narita
{"title":"Guest Editorial Special Issue on 22nd International Workshop on Junction Technologies","authors":"Tetsuo Narita","doi":"10.1109/JEDS.2025.3650320","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3650320","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1320-1320"},"PeriodicalIF":2.4,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11360661","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-21DOI: 10.1109/JEDS.2026.3651876
{"title":"Golden List of Reviewers for 2025","authors":"","doi":"10.1109/JEDS.2026.3651876","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3651876","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1321-1326"},"PeriodicalIF":2.4,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11360100","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper demonstrates an integrated comparator based on a novel platform of GaN-based high electron mobility transistors (HEMTs) with low pressure chemical vapor deposition (LPCVD) SiNx as both gate dielectric and passivation layer. Solving the compatibility issue in device fabrication, both high-performance D-mode and E-mode GaN HEMTs have been realized and then loaded for circuits simulation. With careful determination of each device’s performance, the designed comparator has been constructed, and its comparison range goes from 1 to 3.5 V at VDD ${=}5$ V. Moreover, the comparator achieved a rise time of 754 ns at a driving frequency of 100 kHz, and maintained stable operation even at a high temperature of $200~{^{text {o}}}$ C. The comparator based on the new platform of p-GaN gated HEMTs with LPCVD SiNx passivation provides a new solution for GaN-based power ICs and holds great potential in wide applications.
{"title":"Monolithic Comparators on a Novel Platform of GaN-Based D/E-Mode HEMTs by LPCVD SiNx Passivation Compatible to Gate Dielectrics","authors":"Xinyu Sun;Hongwei Gao;Fangqing Li;Haoran Qie;Xin Chen;Haodong Wang;Yaozong Zhong;Xiaolu Guo;Xinchen Ge;Zhihong Feng;Qian Sun;Hui Yang","doi":"10.1109/JEDS.2026.3655330","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3655330","url":null,"abstract":"This paper demonstrates an integrated comparator based on a novel platform of GaN-based high electron mobility transistors (HEMTs) with low pressure chemical vapor deposition (LPCVD) SiNx as both gate dielectric and passivation layer. Solving the compatibility issue in device fabrication, both high-performance D-mode and E-mode GaN HEMTs have been realized and then loaded for circuits simulation. With careful determination of each device’s performance, the designed comparator has been constructed, and its comparison range goes from 1 to 3.5 V at VDD <inline-formula> <tex-math>${=}5$ </tex-math></inline-formula> V. Moreover, the comparator achieved a rise time of 754 ns at a driving frequency of 100 kHz, and maintained stable operation even at a high temperature of <inline-formula> <tex-math>$200~{^{text {o}}}$ </tex-math></inline-formula>C. The comparator based on the new platform of p-GaN gated HEMTs with LPCVD SiNx passivation provides a new solution for GaN-based power ICs and holds great potential in wide applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"79-84"},"PeriodicalIF":2.4,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11357512","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-15DOI: 10.1109/JEDS.2026.3654157
Ran Ye;Hao Luo;Suyuan Wang;Zhiqiang Hu;Jiaojing Bian;Qiao Kang;Sheng Li;Siyang Liu;Weifeng Sun
The gate-HBM-ESD characteristics of GaN HEMTs integrated with matching networks in package level have been investigated under the positive and negative stresses. For comparison, the GaN HEMTs without matching networks are simultaneously examined to elucidate the influences of the matching networks. Results demonstrate that the matching networks cannot significantly alter the ESD robustness both for the positive and negative stresses. However, after the repetitive non-destructive ESD stresses, pinch-off voltage degradation and input/output impedance shifts are observed, which result in potential mismatch risks for these pre-matched devices. A pinch-off voltage degradation difference is found under the negative stress when compared to the devices without matching networks. During this discharge process, the integrated matching networks can suppress the peak of the gate waveform and the generation of the field-induced damages are reduced.
{"title":"Repetitive Gate-HBM-ESD-Induced Vth Degradation for RF GaN HEMT With Matching Networks","authors":"Ran Ye;Hao Luo;Suyuan Wang;Zhiqiang Hu;Jiaojing Bian;Qiao Kang;Sheng Li;Siyang Liu;Weifeng Sun","doi":"10.1109/JEDS.2026.3654157","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3654157","url":null,"abstract":"The gate-HBM-ESD characteristics of GaN HEMTs integrated with matching networks in package level have been investigated under the positive and negative stresses. For comparison, the GaN HEMTs without matching networks are simultaneously examined to elucidate the influences of the matching networks. Results demonstrate that the matching networks cannot significantly alter the ESD robustness both for the positive and negative stresses. However, after the repetitive non-destructive ESD stresses, pinch-off voltage degradation and input/output impedance shifts are observed, which result in potential mismatch risks for these pre-matched devices. A pinch-off voltage degradation difference is found under the negative stress when compared to the devices without matching networks. During this discharge process, the integrated matching networks can suppress the peak of the gate waveform and the generation of the field-induced damages are reduced.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"41-48"},"PeriodicalIF":2.4,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11352435","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the degradation mechanism of self-aligned top-gate (SA TG) coplanar IGZO thin-film transistors (TFTs) under positive bias temperature stress (PBTS) using low-frequency noise (LFN) analysis. Electrical measurements revealed a positive shift in threshold voltage, increased subthreshold swing, decreased field-effect mobility, and enhanced hysteresis after PBTS. The enhanced unified LFN model, accounting for both channel trap states and gate dielectric traps, successfully explained the observed noise characteristics of fabricated SA TG coplanar IGZO TFTs before and after PBTS. From the extracted trap parameters from LFN analysis, an increase in near-interface trap density and subgap density of states near the conduction band edge was confirmed after PBTS, correlating well with the observed electrical degradation. These results demonstrate that LFN analysis based on the enhanced unified LFN model is an effective diagnostic tool for examining the electrical stress-induced degradation in IGZO TFTs.
{"title":"Investigation of PBTS-Induced Degradation Mechanisms in SA TG Coplanar IGZO TFTs Using Low-Frequency Noise Analysis","authors":"Hyeon-Woo Lee;Su-Hyeon Lee;Dong-Ho Lee;Chae-Eun Oh;Dong-Hwi Son;Chang-Hyeon Kim;Chan-Yong Jeong;Jaeman Jang;Byung-Du Ahn;Jong-Uk Bae;Sang-Hun Song;Hyuck-In Kwon","doi":"10.1109/JEDS.2026.3653818","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3653818","url":null,"abstract":"This study investigates the degradation mechanism of self-aligned top-gate (SA TG) coplanar IGZO thin-film transistors (TFTs) under positive bias temperature stress (PBTS) using low-frequency noise (LFN) analysis. Electrical measurements revealed a positive shift in threshold voltage, increased subthreshold swing, decreased field-effect mobility, and enhanced hysteresis after PBTS. The enhanced unified LFN model, accounting for both channel trap states and gate dielectric traps, successfully explained the observed noise characteristics of fabricated SA TG coplanar IGZO TFTs before and after PBTS. From the extracted trap parameters from LFN analysis, an increase in near-interface trap density and subgap density of states near the conduction band edge was confirmed after PBTS, correlating well with the observed electrical degradation. These results demonstrate that LFN analysis based on the enhanced unified LFN model is an effective diagnostic tool for examining the electrical stress-induced degradation in IGZO TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"36-40"},"PeriodicalIF":2.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347528","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-13DOI: 10.1109/JEDS.2026.3653860
Shishun Yang;Yaxuan Liu;Huiyi Zhang;Hanlin Li;Jun Wang
High-performance GaN-based ultraviolet (UV) photodetectors (PDs) are essential for applications in harsh-environment sensing, space-based UV monitoring, and high-speed optical communications. However, conventional GaN-based p-i-n homojunction UV photodetectors face limitations in responsivity due to significant UV absorption in the p-GaN layer. To address this issue, we propose a novel full depletion (FD) thin-layer structure incorporating a strategically placed 1-nm n-type interlayer at the p–i interface with optimized doping to enhance carrier separation and collection. Results reveal a 27.3% increase in peak responsivity, reaching 0.163 A/W at 360 nm, compared to 0.128 A/W in conventional devices. In addition, the new-structured photodetector exhibits a specific detectivity (D*) of $2.88times 10{^{{13}}}$ Jones, and a low response time of approximately 37 ns. The results of experiments and simulations are highly consistent, verifying the accuracy of the proposed model. Notably, the proposed design maintains excellent electrical performance, with dark current levels comparable to those of traditional architectures, thereby ensuring device stability. The FD-thin doped layer strategy offers a straightforward yet effective route to significantly improve the responsivity of GaN-based UV photodetectors without introducing fabrication complexity or the need for heterojunction integration. This architecture presents a promising pathway toward high-efficiency UV photodetection systems for next-generation applications.
高性能氮化镓基紫外光电探测器（pd）在恶劣环境传感、天基紫外监测和高速光通信应用中至关重要。然而，传统的基于氮化镓的p-i-n同结紫外探测器由于在p-氮化镓层中有明显的紫外吸收而面临响应性的限制。为了解决这一问题，我们提出了一种新的全耗尽（FD）薄层结构，该结构在p-i界面处战略性地放置了1 nm n型夹层，并优化了掺杂，以增强载流子的分离和收集。结果显示，与传统器件的0.128 a /W相比，峰值响应率提高了27.3%，在360 nm处达到0.163 a /W。此外，新结构的光电探测器的比探测率（D*）为$2.88 × 10{^{{13}}}$ Jones，响应时间约为37 ns。实验结果与仿真结果高度吻合，验证了模型的准确性。值得注意的是，所提出的设计保持了优异的电气性能，暗电流水平与传统架构相当，从而确保了器件的稳定性。fd薄掺杂层策略提供了一种直接而有效的途径，可以显着提高氮化镓基紫外光电探测器的响应性，而不需要引入制造复杂性或异质结集成。这种结构为下一代应用的高效紫外光探测系统提供了一条有前途的途径。
{"title":"Enhancing Ultraviolet Responsivity of GaN p-i-n Photodetectors Through Full Depletion Thin-Layer Doping-Induced Carrier Transport Modulation","authors":"Shishun Yang;Yaxuan Liu;Huiyi Zhang;Hanlin Li;Jun Wang","doi":"10.1109/JEDS.2026.3653860","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3653860","url":null,"abstract":"High-performance GaN-based ultraviolet (UV) photodetectors (PDs) are essential for applications in harsh-environment sensing, space-based UV monitoring, and high-speed optical communications. However, conventional GaN-based p-i-n homojunction UV photodetectors face limitations in responsivity due to significant UV absorption in the p-GaN layer. To address this issue, we propose a novel full depletion (FD) thin-layer structure incorporating a strategically placed 1-nm n-type interlayer at the p–i interface with optimized doping to enhance carrier separation and collection. Results reveal a 27.3% increase in peak responsivity, reaching 0.163 A/W at 360 nm, compared to 0.128 A/W in conventional devices. In addition, the new-structured photodetector exhibits a specific detectivity (D*) of <inline-formula> <tex-math>$2.88times 10{^{{13}}}$ </tex-math></inline-formula> Jones, and a low response time of approximately 37 ns. The results of experiments and simulations are highly consistent, verifying the accuracy of the proposed model. Notably, the proposed design maintains excellent electrical performance, with dark current levels comparable to those of traditional architectures, thereby ensuring device stability. The FD-thin doped layer strategy offers a straightforward yet effective route to significantly improve the responsivity of GaN-based UV photodetectors without introducing fabrication complexity or the need for heterojunction integration. This architecture presents a promising pathway toward high-efficiency UV photodetection systems for next-generation applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"49-57"},"PeriodicalIF":2.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347526","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the stress degradation of P-channel Fin Field-Effect Transistor (FinFET) under AC mixed NBTI and HCD stress is studied and compared with the effects of individual NBTI and HCD. In the scope of this study, degradation caused by interface traps becomes more and more dominant with the increase of individual NBTI stress. The more significant degradation observed under individual HCD stress, in comparison to individual NBTI stress at the same voltage, may primarily be attributed to an increase in interfacial traps. The AC mixed stress experiment demonstrates that the interruption of NBTI stress persistence leads to a significant reduction in the defect components within the oxide layer affected by NBTI. Even when NBTI accounts for 85% of the total degradation, the overall extent of degradation remains considerably lower than that observed with single NBTI. Consequently, in AC scenarios, interface traps emerge as the primary contributors to degradation. This finding may hold substantial implications for circuit designers. In practical AC applications, it may reduce the design margin allocated to degradation, thereby avoiding overdesign.
{"title":"Research on Degradation of P-FinFET Under Mixed NBTI and HCD Stress","authors":"Yanghao Wang;Hang Xu;Peng Liao;Jianbin Guo;Qingqing Sun;David Wei Zhang","doi":"10.1109/JEDS.2026.3653934","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3653934","url":null,"abstract":"In this paper, the stress degradation of P-channel Fin Field-Effect Transistor (FinFET) under AC mixed NBTI and HCD stress is studied and compared with the effects of individual NBTI and HCD. In the scope of this study, degradation caused by interface traps becomes more and more dominant with the increase of individual NBTI stress. The more significant degradation observed under individual HCD stress, in comparison to individual NBTI stress at the same voltage, may primarily be attributed to an increase in interfacial traps. The AC mixed stress experiment demonstrates that the interruption of NBTI stress persistence leads to a significant reduction in the defect components within the oxide layer affected by NBTI. Even when NBTI accounts for 85% of the total degradation, the overall extent of degradation remains considerably lower than that observed with single NBTI. Consequently, in AC scenarios, interface traps emerge as the primary contributors to degradation. This finding may hold substantial implications for circuit designers. In practical AC applications, it may reduce the design margin allocated to degradation, thereby avoiding overdesign.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"70-78"},"PeriodicalIF":2.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347527","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1109/JEDS.2025.3648598
{"title":"IEEE ELECTRON DEVICES SOCIETY","authors":"","doi":"10.1109/JEDS.2025.3648598","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3648598","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11319359","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we demonstrate a hybrid ferroelectric charge-trapping gate-stack enhancement-mode GaN tri-gate high electron mobility transistor (FEG-HEMT) featuring a fluorinated HfO2 (F-HfO2) charge trapping layer (CTL), combined with a tri-gate architecture for power device applications. This architecture integrates ferroelectric polarization and charge-trapping mechanisms within a tri-gate nanowire (fin) structure to achieve normally-off operation. Unlike conventional planar HEMTs, the tri-gate configuration exposes the 2-dimensional electron gas (2DEG) channel along the fin sidewalls, enabling effective depletion through trapped charges in the CTL, thereby achieving a high and stable threshold voltage (VTH). There is a possibility that incorporating fluorine into the HfO2 layer reduces oxygen vacancies and dangling bonds, significantly improving the dielectric interface and device reliability. At the dielectric/semiconductor interface, the interface trap density (Dit) was estimated to be $sim ~1times 10{^{{11}}}$ to $1.2times 10{^{{13}}}$ cm${^{text {$mathord {-}$2}}} cdot $ eV${}^{text {$mathord {-}$1}}$ , as extracted using the frequency-dependent conductance method. The tri-gate device demonstrates an impressive VTH of 4.4 ± 0.2 V, I${}_{text {DS-MAX}}$ of 946 ± 10 mA/mm, breakdown voltage (BV) of 768 V, and a high-power figure-of-merit (PFOM) of 973 MW/cm2. Additionally, the device exhibits enhanced time-dependent dielectric breakdown (TDDB) lifetime and gate stress resilience, confirming its superior performance and robustness for high-power applications.
在这项研究中，我们展示了一种混合铁电电荷捕获门堆栈增强模式GaN三栅极高电子迁移率晶体管（fg - hemt），具有氟化HfO2 （F-HfO2）电荷捕获层（CTL），并结合了用于功率器件应用的三栅极结构。该结构将铁电极化和电荷捕获机制集成在三栅极纳米线（鳍）结构中，以实现正常关闭操作。与传统的平面hemt不同，三栅极结构暴露了沿翅片侧壁的二维电子气（2DEG）通道，通过CTL中的捕获电荷实现有效耗尽，从而实现高而稳定的阈值电压（VTH）。在HfO2层中加入氟有可能减少氧空位和悬空键，显著改善介电界面和器件可靠性。在介质/半导体界面处，使用频率相关电导法提取的界面陷阱密度（Dit）估计为$sim ~1乘以10{^{{11}}}$到$1.2乘以10{^{{11}}}$ cm ${^{text {$mathord {-}$2}}} cdot $ eV ${}}^{text {$mathord{-}$1} $。该三栅极器件的VTH为4.4±0.2 V，击穿电压为946±10 mA/mm，击穿电压（BV）为768 V，大功率性能因数（PFOM）为973 MW/cm2。此外，该器件具有增强的时间相关介质击穿（TDDB）寿命和栅极应力恢复能力，证实了其在高功率应用中的优越性能和稳健性。
{"title":"Enhancement Mode GaN Tri-Gate MISHEMT With Fluorinated HfO₂ as Charge Trapping Layer in Hybrid Ferroelectric Gate Stack","authors":"Rahul Rai;Khanh Quoc Nguyen;Hung Duy Tran;Viet Quoc Ho;You Chen Weng;Baquer Mazhari;Hao Chung Kuo;Edward Yi Chang","doi":"10.1109/JEDS.2025.3649208","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3649208","url":null,"abstract":"In this study, we demonstrate a hybrid ferroelectric charge-trapping gate-stack enhancement-mode GaN tri-gate high electron mobility transistor (FEG-HEMT) featuring a fluorinated HfO2 (F-HfO2) charge trapping layer (CTL), combined with a tri-gate architecture for power device applications. This architecture integrates ferroelectric polarization and charge-trapping mechanisms within a tri-gate nanowire (fin) structure to achieve normally-off operation. Unlike conventional planar HEMTs, the tri-gate configuration exposes the 2-dimensional electron gas (2DEG) channel along the fin sidewalls, enabling effective depletion through trapped charges in the CTL, thereby achieving a high and stable threshold voltage (VTH). There is a possibility that incorporating fluorine into the HfO2 layer reduces oxygen vacancies and dangling bonds, significantly improving the dielectric interface and device reliability. At the dielectric/semiconductor interface, the interface trap density (Dit) was estimated to be <inline-formula> <tex-math>$sim ~1times 10{^{{11}}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$1.2times 10{^{{13}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${^{text {$mathord {-}$2}}} cdot $ </tex-math></inline-formula>eV<inline-formula> <tex-math>${}^{text {$mathord {-}$1}}$ </tex-math></inline-formula>, as extracted using the frequency-dependent conductance method. The tri-gate device demonstrates an impressive VTH of 4.4 ± 0.2 V, I<inline-formula> <tex-math>${}_{text {DS-MAX}}$ </tex-math></inline-formula> of 946 ± 10 mA/mm, breakdown voltage (BV) of 768 V, and a high-power figure-of-merit (PFOM) of 973 MW/cm2. Additionally, the device exhibits enhanced time-dependent dielectric breakdown (TDDB) lifetime and gate stress resilience, confirming its superior performance and robustness for high-power applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1313-1319"},"PeriodicalIF":2.4,"publicationDate":"2025-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11317969","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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