Aging and Sintered Layer Defect Detection of Discrete MOSFETs Using Frequency Domain Reflectometry Associated With Parasitic Resistance

IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Device and Materials Reliability Pub Date : 2024-02-08 DOI:10.1109/TDMR.2024.3363713
Minghui Yun;Daoguo Yang;Miao Cai;Haidong Yan;Jiabing Yu;Mengyuan Liu;Siliang He;Guoqi Zhang
{"title":"Aging and Sintered Layer Defect Detection of Discrete MOSFETs Using Frequency Domain Reflectometry Associated With Parasitic Resistance","authors":"Minghui Yun;Daoguo Yang;Miao Cai;Haidong Yan;Jiabing Yu;Mengyuan Liu;Siliang He;Guoqi Zhang","doi":"10.1109/TDMR.2024.3363713","DOIUrl":null,"url":null,"abstract":"Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency \n<inline-formula> <tex-math>$(f_{\\mathrm{ SRF}})$ </tex-math></inline-formula>\n and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations \n<xref>(14)</xref>\n–\n<xref>(15)</xref>\n are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the \n<inline-formula> <tex-math>$f_{\\mathrm{ SRF}}$ </tex-math></inline-formula>\n of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and \n<inline-formula> <tex-math>$R_{\\rm D\\_{}SRF}$ </tex-math></inline-formula>\n. The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"129-141"},"PeriodicalIF":2.5000,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10428070/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency $(f_{\mathrm{ SRF}})$ and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations (14)(15) are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the $f_{\mathrm{ SRF}}$ of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and $R_{\rm D\_{}SRF}$ . The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.
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利用与寄生电阻相关的频域反射仪检测分立 MOSFET 的老化和烧结层缺陷
金属氧化物半导体场效应晶体管(MOSFET)在高热和电应力下会发生疲劳降解。这一过程会导致寄生参数发生变化,而这些变化可通过频域反射仪 (FDR) 检测出来。通过加速老化实验获得的硅和碳化硅 MOSFET 的各种质量状态,采用了频域阻抗分析法对其进行表征。结果表明,随着器件老化,寄生电阻会持续增加。通过确定自谐振频率 $(f_{\mathrm{ SRF}})$下的漏极-源极寄生电阻和不同降解程度 MOSFET 的漏极-源极导通电阻,建立了正线性数值拟合方程 (14)-(15),以预测零直流偏置电压下的 MOSFET 降解。此外,还利用 FDR 技术确定了烧结银层中存在不同大小缺陷的 MOSFET 样品在 $f_{\mathrm{ SRF}}$ 处的漏极寄生电阻。这些结果表明,烧结银层的质量与 $R_{\rm D\_{}SRF}$ 之间存在正相关。所提出的方法是一种有效的功率半导体器件质量筛选技术,无需通电处理。
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来源期刊
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability 工程技术-工程:电子与电气
CiteScore
4.80
自引率
5.00%
发文量
71
审稿时长
6-12 weeks
期刊介绍: The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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