Pub Date : 2026-01-19DOI: 10.1109/TDMR.2026.3653227
{"title":"2025 Index IEEE Transactions on Device and Materials Reliability Vol. 25","authors":"","doi":"10.1109/TDMR.2026.3653227","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3653227","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"1-33"},"PeriodicalIF":2.3,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11357862","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-19DOI: 10.1109/TDMR.2025.3638080
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2025.3638080","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3638080","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11306201","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The combined effect of thermomigration (TM) and electromigration (EM) on the reliability of Cu interconnects is investigated. Package-level EM+TM tests were conducted to understand the impact of temperature gradients on void nucleation and void growth in the presence of electrical currents. Through failure analysis, void nucleation at the via bottom followed by subsequent void growth toward adjacent vias is confirmed. An analytical model is developed to quantify the impact of temperature gradients on EM lifetime. Results indicate that thermal gradients have a more pronounced impact at lower ambient temperatures, reducing EM lifetime by approximately 50% at 100 °C, compared to a 42% reduction at 300 °C. This work enhances the understanding of EM+TM coupling mechanisms and provides a practical model for predicting Cu interconnect reliability under combined stress conditions.
{"title":"Analytical Model for Cu Interconnect Lifetimes Under Combined Thermomigration and Electromigration Stress","authors":"Youqi Ding;Olalla Varela Pedreira;David Coenen;Melina Lofrano;Houman Zahedmanesh;Ahmed Saleh;Ingrid De Wolf;Kristof Croes","doi":"10.1109/TDMR.2025.3629672","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3629672","url":null,"abstract":"The combined effect of thermomigration (TM) and electromigration (EM) on the reliability of Cu interconnects is investigated. Package-level EM+TM tests were conducted to understand the impact of temperature gradients on void nucleation and void growth in the presence of electrical currents. Through failure analysis, void nucleation at the via bottom followed by subsequent void growth toward adjacent vias is confirmed. An analytical model is developed to quantify the impact of temperature gradients on EM lifetime. Results indicate that thermal gradients have a more pronounced impact at lower ambient temperatures, reducing EM lifetime by approximately 50% at 100 °C, compared to a 42% reduction at 300 °C. This work enhances the understanding of EM+TM coupling mechanisms and provides a practical model for predicting Cu interconnect reliability under combined stress conditions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"983-993"},"PeriodicalIF":2.3,"publicationDate":"2025-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through silicon via (TSV) and through glass via (TGV) are critical for advanced chip packaging, enabling vertical interconnections and improving bandwidth. The increase in chip density leads to a dramatic rise in heat generation, which induces the significant coefficient of thermal expansion (CTE) mismatch in TSV and TGV and further induces internal stresses, potentially degrading electrical performance and reliability. This work presented a study of TSV and TGV interconnect structures, focusing on their electrical transmission characteristics under thermal loading, evaluating the reliability differences between TGV and TSV by using electrical transmission characteristics as the metric. The findings reveal that the electrical transmission characteristics of TGV generally outperform those of TSV. Especially, when optimized by increasing signal via spacing and adding additional grounding vias, the characteristics of TGV significantly enhance high-frequency performance. Furthermore, thermal shock measurements indicate that TSV experience rapid transmission characteristics degradation at lower shock cycles, while TGV degrade more slowly even at higher cycles. Based on microstructural analysis, we observe that TSV suffers from cracked insulation layers, leading to current leakage and transmission performance loss; TGV exhibits only minor delamination issues between the RDL and PI that do not significantly impact transmission characteristics. Under high temperature, TSV initially shows improved transmission performance due to air gap formation, but later degrade sharply as copper extrudes and bridges with the silicon substrate. In contrast, under high temperature, TGV exhibit a gradual increase in impedance due to crack expansion within the copper, but this effect remains minimal. TGV not only offers superior transmission performance but also demonstrates greater reliability under thermal loading compared to TSV.
{"title":"Evolution of Electrical Transmission Characteristics in TSV and TGV Interconnect Structures Under Thermal Loading","authors":"Yangyang Zhou;Xiangxiang Zhong;He Diao;Bingxu Ma;Fengzhi Tang;Xing Fu;Ping Lai;Haozhong Wang;Jiahao Liu;Xiaoting Chen;Guoguang Lu;Hongtao Chen;Xiaofeng Yang","doi":"10.1109/TDMR.2025.3628387","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3628387","url":null,"abstract":"Through silicon via (TSV) and through glass via (TGV) are critical for advanced chip packaging, enabling vertical interconnections and improving bandwidth. The increase in chip density leads to a dramatic rise in heat generation, which induces the significant coefficient of thermal expansion (CTE) mismatch in TSV and TGV and further induces internal stresses, potentially degrading electrical performance and reliability. This work presented a study of TSV and TGV interconnect structures, focusing on their electrical transmission characteristics under thermal loading, evaluating the reliability differences between TGV and TSV by using electrical transmission characteristics as the metric. The findings reveal that the electrical transmission characteristics of TGV generally outperform those of TSV. Especially, when optimized by increasing signal via spacing and adding additional grounding vias, the characteristics of TGV significantly enhance high-frequency performance. Furthermore, thermal shock measurements indicate that TSV experience rapid transmission characteristics degradation at lower shock cycles, while TGV degrade more slowly even at higher cycles. Based on microstructural analysis, we observe that TSV suffers from cracked insulation layers, leading to current leakage and transmission performance loss; TGV exhibits only minor delamination issues between the RDL and PI that do not significantly impact transmission characteristics. Under high temperature, TSV initially shows improved transmission performance due to air gap formation, but later degrade sharply as copper extrudes and bridges with the silicon substrate. In contrast, under high temperature, TGV exhibit a gradual increase in impedance due to crack expansion within the copper, but this effect remains minimal. TGV not only offers superior transmission performance but also demonstrates greater reliability under thermal loading compared to TSV.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"966-976"},"PeriodicalIF":2.3,"publicationDate":"2025-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Protecting integrated circuits against electrostatic discharge (ESD) remains a persistent challenge within the semiconductor industry, garnering significant attention from the research and industrial sectors. To effectively discharge substantial ESD current away from sensitive devices, on-chip ESD protection is required to become conductive within mere nanoseconds and then return to an insulated state after the event. Insulator-metal transition (IMT) materials intrinsically possess this property. Little research has been done on the electrostatic discharge characteristics of the well-known IMT material Niobium oxide (NbO2). In this study, we execute transmission line pulse (TLP) assessments on 50-nm ${mathrm { NbO}}_{mathrm { x}}$ vertical construct and analyze ESD characteristics and failure mechanisms utilizing X-ray photoelectron spectroscopy, scanning electron microscopy, etc. The snapback behavior is observed in the device’s TLP I-V curve. The results show the promise of IMT materials for on-chip ESD/EOS protection.
{"title":"Non-Traditional Operational Mechanisms of NbOx-Based Threshold Switching Devices Used on On-Chip ESD Protection","authors":"Jiayi Zhang;Xiaojing Li;Peng Lu;Can Yang;Dong Zhang;Yuepeng Gao;Haoyan Liu;Fei Zhao;Huaizhi Luo;Yongliang Li","doi":"10.1109/TDMR.2025.3624917","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3624917","url":null,"abstract":"Protecting integrated circuits against electrostatic discharge (ESD) remains a persistent challenge within the semiconductor industry, garnering significant attention from the research and industrial sectors. To effectively discharge substantial ESD current away from sensitive devices, on-chip ESD protection is required to become conductive within mere nanoseconds and then return to an insulated state after the event. Insulator-metal transition (IMT) materials intrinsically possess this property. Little research has been done on the electrostatic discharge characteristics of the well-known IMT material Niobium oxide (NbO2). In this study, we execute transmission line pulse (TLP) assessments on 50-nm <inline-formula> <tex-math>${mathrm { NbO}}_{mathrm { x}}$ </tex-math></inline-formula> vertical construct and analyze ESD characteristics and failure mechanisms utilizing X-ray photoelectron spectroscopy, scanning electron microscopy, etc. The snapback behavior is observed in the device’s TLP I-V curve. The results show the promise of IMT materials for on-chip ESD/EOS protection.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"977-982"},"PeriodicalIF":2.3,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-07DOI: 10.1109/TDMR.2025.3618260
Feng Yang;Yihan Liu;Chao Wang;Yang Zhao;Yongfu Li
With power modulation circuits increasingly deployed from terrestrial and marine environments to space, Laterally-Diffused Metal-Oxide Semiconductor (LDMOS) devices, which serve as key components in these circuits, especially when employed as switches, are particularly susceptible to single-event burnout (SEB). To investigate the SEB effects of N-channel LDMOS (nLDMOS) and P-channel LDMOS (pLDMOS) at the circuit-integration level, this letter presents two types of complementary single-event experiments: (i) pulsed-laser testing of complementary LDMOS transistors used as switches in the power modulation circuit, and (ii) heavy-ion testing of an nLDMOS- and pLDMOS- integrated power modulation circuit. The results confirm that pLDMOS exhibits stronger SEB resistance than nLDMOS. This study offers valuable insights for designing radiation-hardened power modulation circuits with integrated LDMOS devices in future aerospace applications.
{"title":"Investigation of Single-Event Burnout in Laterally-Diffused Metal-Oxide Semiconductor for Power Modulation Circuits","authors":"Feng Yang;Yihan Liu;Chao Wang;Yang Zhao;Yongfu Li","doi":"10.1109/TDMR.2025.3618260","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3618260","url":null,"abstract":"With power modulation circuits increasingly deployed from terrestrial and marine environments to space, Laterally-Diffused Metal-Oxide Semiconductor (LDMOS) devices, which serve as key components in these circuits, especially when employed as switches, are particularly susceptible to single-event burnout (SEB). To investigate the SEB effects of N-channel LDMOS (nLDMOS) and P-channel LDMOS (pLDMOS) at the circuit-integration level, this letter presents two types of complementary single-event experiments: (i) pulsed-laser testing of complementary LDMOS transistors used as switches in the power modulation circuit, and (ii) heavy-ion testing of an nLDMOS- and pLDMOS- integrated power modulation circuit. The results confirm that pLDMOS exhibits stronger SEB resistance than nLDMOS. This study offers valuable insights for designing radiation-hardened power modulation circuits with integrated LDMOS devices in future aerospace applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"994-997"},"PeriodicalIF":2.3,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/TDMR.2025.3603779
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2025.3603779","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3603779","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11157723","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/TDMR.2025.3603929
{"title":"Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/TDMR.2025.3603929","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3603929","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"752-753"},"PeriodicalIF":2.3,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11157714","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145028012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/TDMR.2025.3603780
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2025.3603780","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3603780","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11157725","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1109/TDMR.2025.3603930
{"title":"Reliability of Advanced Nodes","authors":"","doi":"10.1109/TDMR.2025.3603930","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3603930","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"754-755"},"PeriodicalIF":2.3,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11157722","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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