Self-Heating Mapping of the Experimental Device and Its Optimization in Advance Sub-5 nm Node Junctionless Multi-Nanowire FETs

Abstract

The junctionless multi-nanowire (JL-MNW) gate-all-around (GAA) field-effect transistor (FET) has become an emerging device in the advanced node of modern semiconductor devices because of its inherent operational mechanism properties. Therefore, in this paper, the Sentaurus TCAD simulator is calibrated with a compact thermal conductivity model using experimentally measured I-V characteristic data of JL-MNW GAA FET and electro-thermal characteristics of the experimental device are mapped into the contour plots. The non-uniform lattice temperature distribution is observed in an experimental device, and the change of peak lattice temperature $(\Delta \text{T}~_{\mathrm{ L,\,max}}$ ) is linearly increased with DC power. Further, in the sub-5nm technology node, the self-heating effect (SHE) is analyzed with variations of device active areas, such as vertical nanowire stacking and poly gate thickness (TP) between two nanowires in a DC operation. This work reveals that the device’s physical parameter variation affects overall performance in sub-5 nm technology nodes, such as ON-current (ION) degradation and delay time. But its thermal reliability is better than the inversion mode GAA FET, such as the peak of lattice temperature (T $_{\mathrm{ L,\,max}}$ ) and thermal resistance (RTH). These are extensively investigated using the Figure of Merit (FoM). Furthermore, the thermal reliability of the experimental device and advanced node JL-MNW GAA FETs are also analyzed in terms of hot carrier injection (HCI) lifetime and bias temperature instability (BTI) lifetime degradation with respect to the $\text{T}_{\mathrm{ L,max}}$ and TP. Considering these results, the junctionless device is expected to be an attractive candidate to improve the performance and reliability in advanced nodes simultaneously.