Utilizing Two Three-Transistor Structures for Designing Radiation Hardened Circuits

Abstract

This paper focuses on two types of three-transistor structures, known as PNN and PPN, which represent the number of PMOS and NMOS transistors in each configuration. These structures are characterized by their unidirectional flip at the output nodes, as they are spatially surrounded by N-type and P-type diffusion regions respectively. This characteristic makes them suitable for designing radiation-hardened circuits, particularly for Single Event Upset (SEU) tolerance. Three dimensional (3-D) simulations demonstrate that when exposed to energetic particles, the node surrounded by N-type diffusion remains immune to 0 $\rightarrow $ 1 flips, while the node surrounded by P-type diffusion remains immune to 1 $\rightarrow $ 0 flips. Additionally, the proposed three-transistor blocks ensure that a conducting path from the voltage supply to ground is never formed, thereby preventing excessive power consumption. Building upon these distinct structures, we propose two area-efficient Single-Node-Upset (SNU) tolerant latches, and two Double-Node-Upset (DNU) recoverable latches. Extensive simulations confirm that our proposed latches, referred to as SNUTL-PNN, SNUTL-PPN, DNURL-PNN and DNURL-PPN, exhibit outstanding self-recovery capability in terms of their output nodes. A comparison with other designs reveals that the latches presented in this paper demonstrate advantages in area and power consumption. Moreover, we applied a variant of PNN and PPN to the dynamic flip-flop, True Single Phase Clock (TSPC), which usually operates with little power and at high speeds. Our introduced hardened scheme occupies minimal area, possess short propagation delays, and exhibit relatively low power consumption under normal operating conditions.