A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Journal of Electronic Testing Pub Date : 2024-03-23 DOI:10.1007/s10836-024-06108-8

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Abstract

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

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英国交通部保证 ReRAM 制造后质量的战略

摘要由于具有 CMOS 制造工艺兼容性、零待机功耗、高可扩展性以及实现高密度存储器和新计算模式的能力，忆阻器已成为补充 CMOS 技术的有前途的候选器件。尽管具有这些优势，但存储器件容易受到制造缺陷的影响，可能导致 CMOS 技术中无法观察到的故障行为，从而大大增加了在制造后测试这些新型器件的难度。本研究提出了一种优化的可测试性设计（DfT）策略，其基础是引入一种 DfT 电路，测量电阻式随机存取存储器（ReRAM）单元的电流消耗，不仅能检测传统故障，还能检测独特故障。新的 DfT 电路通过一个案例研究进行了验证，该案例研究由基于 3x3 字的 ReRAM 和基于 130 纳米预测技术模型 (PTM) 库实现的外围电路组成。所获得的结果证明了所提出的策略在传统和独特故障方面的故障检测能力。此外，本文还评估了与 DfT 电路引入的开销有关的影响，以及工艺变化对拟议 DfT 电路分辨率的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Journal of Electronic Testing

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