Journal of Electronic Testing最新文献

The enhancement of software system quality is achieved through a process called software testing, which is a time and cost-intensive stage of software development. As a result, automating software tests is recognized as an effective solution that can simplify time-consuming and arduous testing activities. Generating test data with maximum branch coverage and fault discovery capability is an NP-complete optimization problem. Various methods based on heuristics and evolutionary algorithms have been suggested to create test suites that provide the most feasible coverage. The main disadvantages of past approaches include inadequate branching coverage, fault detection rate, and unstable results. The main objectives of the current research are to improve the branch coverage rate, fault detection rate, success rate, and stability. This research has suggested an efficient technique to produce test data automatically utilizing a hybrid version of Olympiad Optimization Algorithms (OOA) in conjunction with genetic algorithm (GA) operators theory. Maximum coverage, fault detection capability, and success rate are the main characteristics of produced test data. Various experiments have been conducted on the nine standard benchmark programs. Regarding the results, the suggested method provides 99.92% average coverage, a success rate of 99.20%, an average generation of 5.76, and an average time of 7.97 s. Based on the fault injection experiment’s results, the proposed method can discover about 89% of the faults injected by mutation testing tools such as MuJava.

The challenge caused by redundant feature interference in high-dimensional fault feature data of analog circuits, will undermines the efficacy of conventional analog circuit fault diagnosis techniques, Thus, a novel approach termed Heterogeneous Ensemble Feature Selection (HEFS) is proposed in this paper. This approach is synergistically integrated with the Light Gradient Boosting Machine (LGBM) for pattern recognition, facilitating the prioritization and selection of significant high-dimensional features in analog circuit test data before classification. The methodology commences with the deployment of a heterogeneous ensemble learning strategy for the discernment of crucial high-dimensional features based on their significance. This is followed by the application of the LGBM technique for the pattern recognition classification of the earmarked features. Furthermore, the Tree-structured Parzen Estimator (TPE) optimization method, and five-fold cross-validation, are used for hyperparameter optimization to improve the model’s performance. Diagnostic evaluations are conducted on both University of California Irvine (UCI) datasets and analog circuits to underscore the superior diagnostic precision of the proposed HEFS-LGBM method compared with the existing techniques.

Digital Microfluidic Biochips (DMFBs) are rapidly replacing conventional biomedical analyzers by incorporating diverse bioassay operations with better throughput and precision at a negligible cost. In the last decade, these microfluidic devices have been well anticipated in miscellaneous healthcare applications such as DNA sequencing, drug discovery, drug screening, clinical diagnosis, etc., and other safety-critical fields like air quality monitoring, food safety testing, etc. In view of the application areas, these devices must incorporate the attributes like reliability, accuracy, and robustness. The correctness of a microfluidic device must be ensured through a superior testing technique before it is accepted for use in various applications. In this paper, an optimized fault modelling strategy to detect multiple faults in a digital microfluidic biochip has been introduced by embedding clockwise and anticlockwise movements of droplets using Pebble Traversal (based on Pebble Motion of Graph Theory). The suggested method also calculates traversal time for a fault-free biochip. In addition, this work presents an Advanced Module Sequence Graph-based reconfiguration technique to reinstate the microfluidic device for regular bioassays.

The semiconductor industry has encountered the physical constraints of current semiconductor materials and the impending end of Moore's forecast. The recent edition of the International Roadmap for Devices and Systems reveals that the semiconductor industry is now combining More Moore, More than Moore and Beyond CMOS to explore the possibilities towards emerging nanotechnologies like Quantum Cellular Automata (QCA). The fast-working speed, extremely low energy and high packing density make QCA incredibly appealing. In this work, machine learning-based models are developed to predict the energy dissipation of LT universal logic gates in advance with single-cell displacement defect (SCDD) and cell polarisation. Firstly, the cell-wise energy components of the universal logic gates realised by Layered T (LT) and Majority voter (MV) and logic reduction methodologies are estimated utilising the coherence vector (watt/energy) simulation engine of QCADesigner-E. Then, SCDD is introduced at the output LT universal gates in the horizontal and vertical directions, and consequent deviation in output cell polarisation and energy dissipation are examined. A dataset, namely scdd_polarisation_energy (SPE), is created. In particular, K-Nearest Neighbour, Random Forest and Polynomial Regression-based machine learning (ML) models are found to be competent to anticipate the energy dissipation of LT universal logic gates. In ML models, the SCDD at the output cell and output polarisation are used as estimators, and energy dissipation (in electron Volt) is utilised as a response. These models offer less-complex and ease the energy estimation process in the QCA layout. The models are assessed based on r²-score, mean absolute error (MAE), mean squared error (MSE), and root mean squared error (RMSE).

Dopingless (DLFET) provides better reliability against any physically doped devices. Hence, this paper aims to provide a fair comparison between conventional junctionless (JLFET) and DLFET based ring oscillator (RO) physical unclonable function (PUF) that would lead to a better security solution against any aging constraints. To include aging challenges in our simulation, we stressed conventional JLFET and DLFET against channel hot carrier (CHC) and bias temperature instability (BTI) for 2000 secs. The maximum drain current deviation obtained in JLFET is 20.7 % and that of DLFET is 16 %. Hence, DLFET has more resistance against aging rollbacks than JLFET. Further, 256 staged DL-RO-PUF and JL-RO-PUF are implemented and it is observed that a DL-RO has 60 % better oscillating frequency as compared to a JL-RO. Also, we found that the DL-RO-PUF produce more unique keys than JL-RO-PUF as the inter hamming distance (HD) is 46.9 % for former and 44.6 % for later during normal working conditions. Also, we found that DL-RO-PUF is more reliable than JL-RO-PUF as the maximum intra-HD of former is 3.23 % and of later is 3.66 %. Hence, the novelty of this work is to introduce a highly unique and reliable security solution that helps to provide sustainable electronic systems.

In recent years, the Industrial Internet of Things (IoT) has grown significantly. Automation along with intelligence introduces a slew of cyber risks while implementing industrial digitalization. But, none of the prevailing work focused on provoking alerts to future attacks and protecting the dynamic smart card from malicious attacks.Therefore, a Smooth Scaled Exponential Linear Unit and Reinforcement Learning-based Gated Recurrent Unit (SSELUR-GRU)-based stage identification and dynamic smart card protection are proposed in this paper.Primarily, the data pre-processing is done, and the preprocessed data are balanced using the ADASYN technique. Then, the data is clustered using the CD-KM algorithm for the feasible training of the data. After that, the clustered data is normalized and the patterns of normalized data are analyzed. Further, the important features are chosen by employing the proposed LWSO algorithm for minimizing the processing time of the classifier. Both the obtained optimal features and the patterns are data trained using Log Mish-based Pyramid Net (LM-PN), for classifying the attacked and non-attacked data. In contrast, the input data features and the attacked data are trained by using the proposed SSELUR-GRU for identifying the attack stages.Thus, based on the attack stage, the dynamic card is protected by updating its number, or else the admin is alerted.The experimental outcome stated that when analogized to prevailing methodologies, the proposed method withstands a maximum accuracy of 98.71% and a higher identification rate of 98.21%.

Establishing a general and high-quality testing method for fabricated asynchronous circuits is crucial for the widespread adoption of asynchronous circuits. A full scan design for asynchronous circuits is imperative to address the major issue of manufacturing reliability. To establish a comprehensive testing workflow for asynchronous circuits, verification and validation are required for evaluating the full scan design must be conducted from gate level to chip level. Therefore, this paper proposes layout level circuits corresponding to transistor level scan elements capable of achieving a full scan design for general asynchronous circuits utilizing the Rohm (0.18mathrm {, [mu m]}) process technology. Moreover, a prototype chip fabricated from the taped-out layout level circuits is utilized for verification and validation on both the layout and chip levels. As the verification and validation results at the layout level, the area and delay overhead against the original C-element and the scan C-elements were evaluated. Furthermore, the prototype real chip implementing the proposed scan C-elements was mounted onto a chip tester for dynamic verification by simulation, and the functional delay was measured by observing the signals with an oscilloscope. The usefulness of the proposed scan C-elements in the real chip has shown that it can be utilized as a library to realize a full scan design of asynchronous circuits.

Traditional ADC dynamic parameter testing algorithms have high requirements for signal amplitude, purity, and coherence, which not only have high test cost but also low efficiency. Therefore, a set of ADC dynamic parameter testing algorithms was developed to relax the testing conditions. The algorithm fits the clipped signal through an interpolated fitting algorithm to obtain the residual sequence to relax the input signal amplitude limit; reduces the parameter fitting error and spectral leakage on the spurious components by data preprocessing, restores the ADC's own parameters by external noise cancellation method. Under 14-bit signal source, 5.2-V amplitude, and 0.3 leakage, the signal-to-noise ratio, signal-to-noise-and-distortion ratio, effective-number- of-bits, and total-harmonic-distortion of the 16-bit ADC chip 7606 have errors from the typical values of 0.39 dB, 0.23 dB, 0.16 bit, and 7.24 dB, respectively, which are within the manual range. The results demonstrate the functionality and robustness of the proposed relaxed testing algorithm.

With the increasing interest in embedding digital devices in safety-critical cyber-physical systems (CPSs), such as industrial automation, aerospace, and automotive industries, attention has been directed toward proposing verifiable and reliable architectures. Prominent levels of formal verification and fault-tolerance are a requirement in dependable CPS systems to ensure system design meet the specifications and verify safety properties. In this paper, a novel formal verifiable and fault-tolerant hardware architecture uses the concepts of state machine, verification, and fault-tolerance as a foundation is developed. It is divided into four models: analysis model includes the functional requirements defined by the user, design model, the finite state machine is utilized to model the systems behavior which is tested by the NuSMV checker tool, implementation model simulates test cases on waveforms to validate the design against the requirements and verification model verifies functional and critical properties using mathematical formal linear time and computation tree logic to prove compliance with requirements and detect errors. The system uses temporal logic to formulate the required properties for a railway interlocking system (RIS) as a case study and symbolic model verifier (SMV) to demonstrate the correct execution. From the simulation results, the effectiveness of the architecture is proved for verifying critical properties and detecting design faults through majority voting circuits. The proposed architecture has been synthesized in the Altera FPGA programmable chip with logic elements 33%, 52% area overhead, and frequency as 100 MHz. The system does meet its reliability requirements with the lowest reliability 91.333687 x ({10}^{-2}) and failure rate 0.2 failure per hour at time 60 min. Finally, we think that adopting this architecture will enhance the trustworthiness and certification of CPS systems.

Mixed-signal applications have emerged as a significant trend in the semiconductor industry, with considerable efforts directed towards developing fast and accurate designs that integrate both analog and digital components. However, mixed-signal verification presents a major challenge due to the slow verification time and limited robustness of traditional verification techniques. In this study, a verification architecture for a successive-approximation register (SAR) analog-to-digital converter (ADC) real number model (Real Number Modeling – RNM) using SystemVerilog is presented, which utilizes an efficient UVM-based methodology. The proposed approach combines the UVM capabilities with the RNM model of the SAR ADC to generate a reusable, fast, and robust verification environment with a reduced time-to-market. The testbench creation and simulation were carried out using Cadence Xcelium. The proposed verification architecture employs constrained-random stimulus generation, analog assertions, and coverage metrics to enhance verification effectiveness. Additionally, aim of this work is to emphasize on the RNM efficiency with SystemVerilog, and apply its modeling capabilities for a SAR ADC. The presented real number model was compared to a Verilog-AMS model. The conducted experiments provided evidence that the proposed RNM model exhibits a significant improvement in simulation efficiency compared to previous works documented in the literature (simulation time was at 0.5 s, compared to a Verilog-AMS reference model’s simulation at 20 s). This improvement in efficiency is achieved without compromising on the accuracy of the simulation, ensuring that the model maintains a satisfactory level of precision.