Channel engineering for optimizing the electro-thermal characteristics in p-type GAA nanosheet transistors

Abstract

In this paper, we report simulation results for capacitance–voltage characteristics and temperature distribution in the cross-section of p-type gate-all-around nanosheet channel using an in-house developed numerical simulator. The effects of material, channel width, and crystallographic orientation on electrical and thermal properties of p-type nanosheet transistor are comprehensively investigated. The effect of channel engineering is analyzed, by evaluating density-of-states, hole density, current densities as well as distributions of temperature in the channel cross-section. Finally, the thermal reliability of the device is addressed in terms of thermal resistance. The density-of-states and the hole density distribution at the oxide/channel interface can well explain the effective intrinsic capacitance obtained from the simulation. The better uniformity of the hole density distribution across the cross-section of (110)/[001] channel, shows good promise for less performance fluctuation in terms of the thermal reliability issue.