On the voltage dependent series resistance, interface traps, and conduction mechanisms in the Al/(Ti-doped DLC)/p-Si/Au Schottky Diodes (SDs)

Abstract

In this study, Al-(Ti:DLC)-pSi/Au Schottky Diode (SD) was manufactured instead of conventional metal-semiconductor (MS) with/without an insulator-layer and then several fundamental electrical characteristics such as ideality-factor (n), barrier-height , series-shunt resistances (Rs, Rsh), concentration of acceptor-atoms (Na), and depletion-layer width (Wd), were derived from the forward-reverse bias current-voltage (I-V), capacitance and conductance as a function of voltage (C/G-V) data using various calculation-methods. Semi logarithmic IF-VF plot shows a linear behavior at lower-voltages and then departed from linearity as a result of the influence of series resistance/Rs and organic-interlayer. Three linear regions can be seen on the double-logarithmic IF-VF plot. with different slopes (1.28, 3.14, and 1.79) in regions with low, middle, and high forward bias, which are indicated that Ohmic, trap charge limited current (TCLC), and space charge limited current (SCLC), respectively. Energy dependent surface states (Nss) vs (Ess-Ev) profile was also obtained from the Card-Rhoderick method by considering voltage dependence of n and and they were grown from the mid-gap energy up to the semiconductor's valance band (Ev). To see the impact of Rs for 1 MHz, the measured C/G-V graphs were amendment. All results are indicated that almost all electrical parameters and conduction mechanism are quite depending on Rs, Nss, and calculation method due the voltage dependent of them.