Design and analysis of Voltage-Gated Spin-Orbit Torque (VgSOT) Magnetic Tunnel Junction based Non-Volatile Flip Flop design for Low Energy Applications

Abstract

In this paper, a Voltage-gated Spin-Orbit Torque based non-volatile flip-flop design has been discussed. Theflip-flop consists of a conventional CMOS master latch used in normal operations, and a VgSOT-MTJ basedslave latch has been considered for interim data saving during power-gating. The current circuit uses the samewrite current to write data into two magnetic tunnel junctions, saving 50% of storing energy. The proposedNVFF circuit has been simulated using Cadence Virtuoso 45nm. The performance parameters like energyconsumption and delay during restore and store operations of VgSOT-MTJ based NVFF circuit have beenanalyzed in this paper and compared with SOT-MTJ based and STT-MTJ based NVFF circuits. Simulationresults show that for the switching delay, VgSOT-MTJ based NVFF performs 40% and 58% better than SOT-MTJ NVFF and STT-MTJ based NVFFs, respectively during storing mode and 83% and 88% better than SOT-MTJ and STT-MTJ based NVFFs during restoring mode. In terms of energy consumption, during storingmode, VgSOT-MTJ based NVFF consumes 84% less energy than SOT-MTJ NVFF and 90 % less energy thanSTT-MTJ based NVFFs. During restoring mode, VgSOT-MTJ based NVFF consumes 70% and 80% lessenergy than SOT-MTJ NVFF and STT-MTJ, respectively.