{"title":"Multicore Packet Distribution Method Using Multicore Network Interface Card Based on Tile-gx72 Network Processor","authors":"W. Choi, Sang Ju Lee, Jong Oh Kim, S. Choi","doi":"10.23919/ICACT60172.2024.10471931","DOIUrl":null,"url":null,"abstract":"We propose a data plane acceleration technology to deliver data from the network to the host system in a high-performance computing environment. In the fourth industrial revolution, server systems are developing into high-performance computing systems through convergence with maj or technologies such as IoT, cloud, AI, and self-driving cars. The 4th industrial revolution is the convergence of various technologies and IT, requiring various flows and large amounts of data to be processed on servers. When transferring packets from the network interface card to the host server, packet processing in kernel space has a large overhead. Additionally, for fast packet processing by the host server, packets must be processed according to core affinity. Therefore, we propose a load balancing data transmission method to 48 cores based on Tile-Gx72 network processor to transfer data from the network interface card to the host CPU by kernel bypass in a multi-core-based high-performance server system. In addition, the performance of the 48 cores-based load balancing data transmission system based on the Tile-Gx72 network processor is confirmed through implementation.","PeriodicalId":518077,"journal":{"name":"2024 26th International Conference on Advanced Communications Technology (ICACT)","volume":"17 10","pages":"350-353"},"PeriodicalIF":0.0000,"publicationDate":"2024-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2024 26th International Conference on Advanced Communications Technology (ICACT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ICACT60172.2024.10471931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We propose a data plane acceleration technology to deliver data from the network to the host system in a high-performance computing environment. In the fourth industrial revolution, server systems are developing into high-performance computing systems through convergence with maj or technologies such as IoT, cloud, AI, and self-driving cars. The 4th industrial revolution is the convergence of various technologies and IT, requiring various flows and large amounts of data to be processed on servers. When transferring packets from the network interface card to the host server, packet processing in kernel space has a large overhead. Additionally, for fast packet processing by the host server, packets must be processed according to core affinity. Therefore, we propose a load balancing data transmission method to 48 cores based on Tile-Gx72 network processor to transfer data from the network interface card to the host CPU by kernel bypass in a multi-core-based high-performance server system. In addition, the performance of the 48 cores-based load balancing data transmission system based on the Tile-Gx72 network processor is confirmed through implementation.