A compact 27 dBm triple-stack power amplifier for 13 GHz operation in CMOS-SOI

Sravya Alluri, Vincent Leung, Peter Asbeck
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Abstract

Power amplifiers at 13 GHz are attracting attention for possible use in 6G wireless systems, and the comparison between different transistor technologies that could be applied is an emerging research focus. Relative to 5G mm-wave power amplifiers, higher output power (up to 30-35 dBm), high efficiency and high linearity are important requirements for 6G. This paper focuses on design considerations for high power CMOS-SOI technology at 13 GHz, including scaling issues relative to the well-studied 28GHz designs. A single-stage, single-ended pMOS amplifier is reported which achieves Psat=27 dBm and peak PAE=43%, in a small area (0.33 mm2 excluding pads). These are believed to be the highest reported results for CMOS, although this band has received relatively little attention to date.
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采用 CMOS-SOI 技术的紧凑型 27 dBm 三叠层功率放大器,可在 13 GHz 频率下工作
13 GHz 功率放大器因可能用于 6G 无线系统而备受关注,对可应用的不同晶体管技术进行比较是一个新兴的研究重点。与 5G 毫米波功率放大器相比,更高的输出功率(高达 30-35 dBm)、高效率和高线性度是 6G 的重要要求。本文重点介绍 13 GHz 高功率 CMOS-SOI 技术的设计考虑因素,包括相对于经过充分研究的 28 GHz 设计的扩展问题。本文报告了一种单级、单端 pMOS 放大器,它在较小的面积(0.33 平方毫米,不包括焊盘)内实现了 Psat=27 dBm 和峰值 PAE=43%。尽管迄今为止这一频段受到的关注相对较少,但这些结果被认为是 CMOS 的最高成果。
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