A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection

Abstract

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability.