Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht
{"title":"Chemical Mechanical Polishing of Single-Crystalline Diamond Epitaxial Layers for Electronics Applications","authors":"Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht","doi":"10.1109/TSM.2024.3383287","DOIUrl":null,"url":null,"abstract":"For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (<\n<inline-formula> <tex-math>$1 ~\\mu \\text{m}$ </tex-math></inline-formula>\n), doped epitaxial SCD layers with very low (<1> <tex-math>$4.5 mm^{2}$ </tex-math></inline-formula>\n area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"190-198"},"PeriodicalIF":2.3000,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Semiconductor Manufacturing","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10485527/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (<
$1 ~\mu \text{m}$
), doped epitaxial SCD layers with very low (<1> $4.5 mm^{2}$
area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications.
期刊介绍:
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.