Improving the Reliability of Through Silicon Vias: Reducing Copper Protrusion by Artificial Defect Manipulation and Annealing

Abstract

Through silicon vias (TSVs) are a critical technology for manufacturing three-dimensional stacked structure of semiconductor packages by forming holes that penetrate silicon wafers and vertically interconnect multiple wafers. Typically, TSVs are created by drilling via holes in wafers and filling their interiors using copper electroplating processes. Subsequently, the wafers are exposed to high-temperature environments during the back-end-of-line (BEOL) process. However, improper copper electroplating conditions can form defects, such as voids and seams, within TSVs, while the high temperature of the BEOL process induces copper protrusion phenomena. These defects and copper protrusion degrade the reliability of TSV. In this brief, copper protrusion behavior, which is a direct cause of reliability degradation in TSVs, was mitigated by experimentally exploring the seam defects that can occur during the TSV filling process. Subsequent annealing processes were applied to remove the seam defects based on the copper-grain growth. The copper protrusion height was analyzed based on the size of the seam defects and annealing temperature. From the proposed process in this brief, the copper protrusion heights of TSVs without and with seam defects were confirmed to be 1.531 and $1.289~\mu \text{m}$ , respectively, representing an improvement of approximately 15.81%.