TDDB Lifetime Reduction From Charging Damage in a 3D Vertical NAND Memory Technology

Abstract

Plasma Induced Damage (PID) testing methodology is applied to a Vertical Floating-Gate 3D NAND Memory Technology with CMOS under Array (CuA) and detected lifetime effects are reported for the first time. Revealing Constant Current Stresses (CCS) at elevated temperature of 95°C are performed to identify process charging risks. The effect on transistor dielectric breakdown lifetimes from PID induced defects are quantified by a Constant Voltage Stress (CVS) test methodology and modeled by combining intrinsic and extrinsic failure distributions scaled by antenna size. To determine the voltage dependence of the early fails, a larger sample size is stressed at varying gate stress voltages. The tests show the same intrinsic power law voltage acceleration while for larger antennas the extrinsic branches increase with reduced gate stress voltage. The empirical bimodal TDDB model with added intrinsic/extrinsic power law terms for the gate stress voltage can describe the behavior with high accuracy. A physical model using the gate current voltage characteristics and the antenna area ratios as inputs is developed, which describes the behavior also with good agreement. Probing pad charging damage effects are further analyzed by TDDB tests on capacitor structures of varying gate dielectric areas for n- and pMOS devices of different dielectric thicknesses.