21T Ternary Full Adder Based on Capacitive Threshold Logic and Carbon Nanotube FETs

Abstract

The reduction in transistor count has long been a big challenge and an ongoing objective in the design of Ternary Full Adders (TFAs). Capacitive Threshold Logic (CTL) is a well-known logic style requiring a small number of transistors to implement a circuit. This paper presents a novel CTL TFA that utilizes only 21 transistors, three of which function as capacitors. Reducing the number of transistors can achieve a more compact adder cell with fewer internal wires. Simulations by HSPICE and 32nm CNFET technology demonstrate promising results for the new TFA compared to previous competitors. It produces the output carry at the fastest speed and also utilizes six fewer transistors and three fewer nets than its closest competitor with the fewest elements. When a comprehensive evaluation factor including delay, power, and area is considered, the proposed design exhibits a performance superiority of 45.1% and 21.4% compared to the previous top-performing CTL and non-CTL designs, respectively.