Pub Date : 2024-12-31DOI: 10.1109/TNANO.2024.3524567
Ju-Won Yeon;Hyo-Jun Park;Eui-Cheol Yun;Moon-Kwon Lee;Tae-Hyun Kil;Yong-Sik Kim;Jun-Young Park
Recently, deuterium annealing at a reduced temperature range of 300 °C has been proposed to enhance SiO2 gate dielectrics and the Si/SiO2 interface, thereby improving device reliability. As a further investigation into deuterium annealing, for the first time this study compared deuterium absorption characteristics with various SiO2 dielectrics formed by wet oxidation, dry oxidation, low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). Deuterium annealing can also be used to reduce the roughness and improve the uniformity of SiO2 dielectric films. Surface roughness of various samples was measured and quantitatively compared using atomic force microscopy (AFM) after deuterium annealing.
{"title":"Improvement of Surface Roughness in SiO2 Thin Films via Deuterium Annealing at 300 °C","authors":"Ju-Won Yeon;Hyo-Jun Park;Eui-Cheol Yun;Moon-Kwon Lee;Tae-Hyun Kil;Yong-Sik Kim;Jun-Young Park","doi":"10.1109/TNANO.2024.3524567","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3524567","url":null,"abstract":"Recently, deuterium annealing at a reduced temperature range of 300 °C has been proposed to enhance SiO<sub>2</sub> gate dielectrics and the Si/SiO<sub>2</sub> interface, thereby improving device reliability. As a further investigation into deuterium annealing, for the first time this study compared deuterium absorption characteristics with various SiO<sub>2</sub> dielectrics formed by wet oxidation, dry oxidation, low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). Deuterium annealing can also be used to reduce the roughness and improve the uniformity of SiO<sub>2</sub> dielectric films. Surface roughness of various samples was measured and quantitatively compared using atomic force microscopy (AFM) after deuterium annealing.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"54-58"},"PeriodicalIF":2.1,"publicationDate":"2024-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The power and energy densities of a Supercapacitor (SC) is largely dictated by the accessibility of the nano-porous area of the electrode to the electrolyte ions. Carbon nanotubes (CNT) have high electrical conductivity, and more importantly, may be grown into architectures with high surface area. However, this is not easy to achieve in practice. CNT electrodes are fabricated by chemical vapor deposition (CVD), after a metal catalyst layer is coated on a current collector. In this work, the control of the metal catalyst layer, by varying the dip-coating time and CVD process parameters, is shown to be crucial to pore morphology and consequent SC performance. The dip-coating time is adjusted to obtain thin and uniform coating. Further, optimum reduction of the nickel layer with hydrogen is required to produce thin CNTs with adequate inter-tube separation that facilitate ion accessibility within the pores. The height of the CNT forest is also optimized to prevent decrease in specific capacitance due to reduced accessibility. Proper optimization of the process parameters results in a pore morphology conductive to ion diffusion, and simultaneous improvement in energy and power density.
{"title":"On the Importance of the Metal Catalyst Layer to the Performance of CNT-Based Supercapacitor Electrodes","authors":"Kingshuk Chatterjee;Vinay Kumar;Prabhat Kumar Agnihotri;Sumit Basu;Nandini Gupta","doi":"10.1109/TNANO.2024.3523412","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3523412","url":null,"abstract":"The power and energy densities of a Supercapacitor (SC) is largely dictated by the accessibility of the nano-porous area of the electrode to the electrolyte ions. Carbon nanotubes (CNT) have high electrical conductivity, and more importantly, may be grown into architectures with high surface area. However, this is not easy to achieve in practice. CNT electrodes are fabricated by chemical vapor deposition (CVD), after a metal catalyst layer is coated on a current collector. In this work, the control of the metal catalyst layer, by varying the dip-coating time and CVD process parameters, is shown to be crucial to pore morphology and consequent SC performance. The dip-coating time is adjusted to obtain thin and uniform coating. Further, optimum reduction of the nickel layer with hydrogen is required to produce thin CNTs with adequate inter-tube separation that facilitate ion accessibility within the pores. The height of the CNT forest is also optimized to prevent decrease in specific capacitance due to reduced accessibility. Proper optimization of the process parameters results in a pore morphology conductive to ion diffusion, and simultaneous improvement in energy and power density.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"48-53"},"PeriodicalIF":2.1,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142940840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-25DOI: 10.1109/TNANO.2024.3522371
Tsung-Ying Yang;Mei-Yan Kuo;Jui-Sheng Wu;Yan-Kui Liang;Rahul Rai;Shivendra K. Rathaur;Edward Yi Chang
This study tested fluorine doping on various regions of the ferroelectric charge trap gate stack (FEG stack). Fluorine doping effectively reduces oxygen vacancies in the dielectric layer, thus reducing leakage current and stabilizing charge in the dielectric layer. Moreover, fluorine doping can passivate the dangling bonds at the interface and increase the ability of trapping carriers in the trap layer. The FEG stack comprises a tunnel oxide layer (TL), a charge trap layer (CTL), and a ferroelectric layer (FE). Four types of devices were fabricated: undoped, doping in TL, doping in CTL, and doping in both TL and CTL, to investigate the impact of fluorine doping on the FEG gate stack. Devices doping in TL and CTL demonstrated superior performance, achieving the highest V th