R. Manera, R. Ballabriga, J. Mauricio, J. Kaplon, A. Paternò, F. Bandi, S. Gómez, A. Pulli, S. Portero, J. Silva, F. Keizer, C. D’Ambrosio, M. Campbell, D. Gascón
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引用次数: 0
Abstract
This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed
in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout
detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers
candidates for Run 5. The front-end (FE) stage has an input impedance below 50 Ω and an
input dynamic range from 5 μA to 5 mA with a power consumption of ∼5 mW/channel. The chip
includes a Leading Edge Comparator (LED) and a Constant Fraction Discriminator (CFD) for time
pick-off and a Time-to-Digital Converter (TDC) for digitization.
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