Validation of the 65 nm TPSCo CMOS imaging technology for the ALICE ITS3

C. Ferrero
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Abstract

During the next Long Shutdown (LS3) of the LHC, planned for 2026, the innermost three layers of the ALICE Inner Tracking System will be replaced by a new vertex detector composed of curved ultra-thin monolithic silicon sensors. The R&D initiative on monolithic sensors of the CERN Experimental Physics Department, in cooperation with the ALICE ITS3 upgrade project, prepared the first submission of chip designs in the TPSCo 65 nm technology, called MLR1 (Multi Layer Reticle). It contains four different test structures with different process splits and pixel designs. These proceedings illustrate the first validation of the technology in terms of pixel performance and radiation hardness.
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为 ALICE ITS3 验证 65 纳米 TPSCo CMOS 成像技术
在计划于 2026 年进行的下一次大型强子对撞机长期关闭(LS3)期间,ALICE 内部跟踪系统的最内侧三层将被由曲面超薄单片硅传感器组成的新型顶点探测器取代。欧洲核子研究中心实验物理部的单片传感器研发计划与 ALICE ITS3 升级项目合作,准备了第一份采用 TPSCo 65 纳米技术的芯片设计,名为 MLR1(多层视网膜)。它包含四个不同的测试结构,具有不同的工艺分割和像素设计。这些程序说明了该技术在像素性能和辐射硬度方面的首次验证。
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