Cryogenic Small Dimension Effects and Design-Oriented Scalable Compact Modeling of a 65-nm CMOS Technology

Abstract

This paper presents the cryogenic characterization and compact modeling of thin-oxide MOSFETs in a standard 65-nm Si-bulk CMOS technology. The influence of both short and narrow channel effects at extremely low temperature on key device parameters such as threshold voltage and ON current is highlighted, and the performance of this technology node for cryogenic analog circuit design is discussed. It is then demonstrated, for the widest range of gate geometries in literature, that the BSIM4 parameter editing approach can be successfully used to model small dimension effects at cryogenic temperature. In the absence of cryogenic foundry models, the robustness and simplicity of this modeling technique make it a preferred method to quickly build a design-oriented, fully scalable SPICE compact model. This restores complete freedom in device sizing for cryogenic analog circuit design.