TAFT: Thermal-Aware Hybrid Fault-Tolerant Technique for Multicore Embedded Systems

Abstract

To achieve high reliability, fault-tolerance techniques are exploited, but they may increase power consumption and temperature beyond safe limits. Therefore, power-aware fault-tolerance techniques should be used to manage power and temperature issues. We tolerate both permanent and transient faults through hybrid fault-tolerance techniques. In this letter, at first, we investigate how much power and temperature are increased when a hybrid fault-tolerance technique is applied to multicore embedded systems. Then, we propose a peak-power-aware hybrid fault-tolerant technique to meet the temperature constraint. Transient-temperature-based safe power (T-TSP) is a new power budgeting technique whose calculation is based on the current temperature of the processing core. Assigning dynamic budgets through T-TSP to processing cores allows us to effectively reach the full performance of processing cores. Experiments show that our proposed method reduces peak power and energy consumption on average by 13.5% (up to 50.7%) and 41.8% (up to 67.4%), respectively and improves the schedulability on average by 6.8% (up to 22.4%) compared to state-of-the-art methods while meeting the system reliability target.