Pub Date : 2024-12-05DOI: 10.1109/LES.2024.3439552
Zhao Yang;Haoyang Wang;Qingshuang Sun
Federated learning (FL) on the edge devices must support continual learning (CL) to handle continuously evolving the data and perform the model training in an energy-efficient manner to accommodate the devices with limited computational and energy resources. This letter proposes an energy-efficient personalized federated CL (FCL) framework for the edge devices. The network structure on each device is divided into parts for retaining old knowledge and learning new knowledge, training only part of the model to reduce overhead. A data-free parameter selection approach selects important parameters from the trained model to retain old knowledge. During new task learning, a federated search method determines a resource-adaptive personalized model structure for each device. Experimental results demonstrate that our method can effectively support FCL in an energy-efficient manner on the edge devices.
{"title":"Energy-Efficient Personalized Federated Continual Learning on Edge","authors":"Zhao Yang;Haoyang Wang;Qingshuang Sun","doi":"10.1109/LES.2024.3439552","DOIUrl":"https://doi.org/10.1109/LES.2024.3439552","url":null,"abstract":"Federated learning (FL) on the edge devices must support continual learning (CL) to handle continuously evolving the data and perform the model training in an energy-efficient manner to accommodate the devices with limited computational and energy resources. This letter proposes an energy-efficient personalized federated CL (FCL) framework for the edge devices. The network structure on each device is divided into parts for retaining old knowledge and learning new knowledge, training only part of the model to reduce overhead. A data-free parameter selection approach selects important parameters from the trained model to retain old knowledge. During new task learning, a federated search method determines a resource-adaptive personalized model structure for each device. Experimental results demonstrate that our method can effectively support FCL in an energy-efficient manner on the edge devices.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"345-348"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An alarming increase in hypertension is a hazard to global health that poses severe implications for the body’s vital organs. To prevent serious repercussions, hypertension should be monitored continuously for early detection. It is well known that physiological signals, such as the photoplethysmogram (PPG) and electrocardiogram (ECG), carry essential information about the vitals of the human body. Considering this, numerous machine learning-based models based on ECG-PPG have been proposed for monitoring hypertension; however, such models are “non-explainable” and lack clinical interpretation. This work proposes a formal method-based runtime verification approach for hypertension monitoring using ECG and PPG sensing, which is explainable. The pulse arrival time (PAT) feature extracted using both signals is employed to implement a decision tree to infer hypertension patterns/policies defined in PAT, based on which a runtime monitor is synthesized to classify hypertension. Using the MIMIC II dataset, the proposed scheme’s performance is assessed, and the accuracy, sensitivity, and specificity are determined to be 95.7%, 93.9%, and 97.6%, respectively.
{"title":"An Explainable and Formal Framework for Hypertension Monitoring Using ECG and PPG","authors":"Abhinandan Panda;Ayush Anand;Srinivas Pinisetty;Partha Roop","doi":"10.1109/LES.2024.3443449","DOIUrl":"https://doi.org/10.1109/LES.2024.3443449","url":null,"abstract":"An alarming increase in hypertension is a hazard to global health that poses severe implications for the body’s vital organs. To prevent serious repercussions, hypertension should be monitored continuously for early detection. It is well known that physiological signals, such as the photoplethysmogram (PPG) and electrocardiogram (ECG), carry essential information about the vitals of the human body. Considering this, numerous machine learning-based models based on ECG-PPG have been proposed for monitoring hypertension; however, such models are “non-explainable” and lack clinical interpretation. This work proposes a formal method-based runtime verification approach for hypertension monitoring using ECG and PPG sensing, which is explainable. The pulse arrival time (PAT) feature extracted using both signals is employed to implement a decision tree to infer hypertension patterns/policies defined in PAT, based on which a runtime monitor is synthesized to classify hypertension. Using the MIMIC II dataset, the proposed scheme’s performance is assessed, and the accuracy, sensitivity, and specificity are determined to be 95.7%, 93.9%, and 97.6%, respectively.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"405-408"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/LES.2024.3446948
Mozhgan Navardi;Edward Humes;Tinoosh Mohsenin
Efficiently deploying deep neural networks on resource-limited embedded systems is crucial to meet real-time and power consumption requirements. Utilizing metareasoning as a higher-level controller along with tiny machine learning (TinyML) can enhance energy efficiency and reduce latency on such systems by overseeing available resources. This study introduces MetaTinyML, a comprehensive metareasoning framework for self-guided navigation on TinyML platforms. The framework adapts its decision-making process by factoring in environmental changes to select the most suitable algorithms for the current scenario. Implementation of MetaTinyML on an NVIDIA Jetson Nano 4-GB system integrated with a Jetbot ground vehicle demonstrated up to 50% power consumption enhancement. View a video demonstration of the MetaTinyML framework at: Video.
{"title":"MetaTinyML: End-to-End Metareasoning Framework for TinyML Platforms","authors":"Mozhgan Navardi;Edward Humes;Tinoosh Mohsenin","doi":"10.1109/LES.2024.3446948","DOIUrl":"https://doi.org/10.1109/LES.2024.3446948","url":null,"abstract":"Efficiently deploying deep neural networks on resource-limited embedded systems is crucial to meet real-time and power consumption requirements. Utilizing metareasoning as a higher-level controller along with tiny machine learning (TinyML) can enhance energy efficiency and reduce latency on such systems by overseeing available resources. This study introduces MetaTinyML, a comprehensive metareasoning framework for self-guided navigation on TinyML platforms. The framework adapts its decision-making process by factoring in environmental changes to select the most suitable algorithms for the current scenario. Implementation of MetaTinyML on an NVIDIA Jetson Nano 4-GB system integrated with a Jetbot ground vehicle demonstrated up to 50% power consumption enhancement. View a video demonstration of the MetaTinyML framework at: Video.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"393-396"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/LES.2024.3443205
Ping-Xiang Chen;Dongjoo Seo;Nikil Dutt
Flexible data placement (FDP) is an emerging interface within the NVM express (NVMe) storage standard, aiming to decrease write amplification factor (WAF) in solid state drives (SSDs) through explicit user-controlled data placement. Currently, the FDP ecosystem burdens embedded software programmers with low-level systems programming to efficiently deploy FDP SSDs. We propose FDPFS, a file system that elevates the abstraction to file systems by exposing FDP SSDs as directories to which programmers can easily group and direct semantically similar data for user-controlled data placement. Under the hood, FDPFS performs the tedious low-level tasks of interfacing and assigning these semantically grouped data to different SSD erase blocks to reduce WAF, and improve overall SSD performance and lifetime. Our case study on the filebench benchmark demonstrates that our FDPFS prototype not only eases explicit data placement, but also yields up to 34% reduction in the SSD WAF which promises improved overall performance and lifetime of the SSD.
{"title":"FDPFS: Leveraging File System Abstraction for FDP SSD Data Placement","authors":"Ping-Xiang Chen;Dongjoo Seo;Nikil Dutt","doi":"10.1109/LES.2024.3443205","DOIUrl":"https://doi.org/10.1109/LES.2024.3443205","url":null,"abstract":"Flexible data placement (FDP) is an emerging interface within the NVM express (NVMe) storage standard, aiming to decrease write amplification factor (WAF) in solid state drives (SSDs) through explicit user-controlled data placement. Currently, the FDP ecosystem burdens embedded software programmers with low-level systems programming to efficiently deploy FDP SSDs. We propose FDPFS, a file system that elevates the abstraction to file systems by exposing FDP SSDs as directories to which programmers can easily group and direct semantically similar data for user-controlled data placement. Under the hood, FDPFS performs the tedious low-level tasks of interfacing and assigning these semantically grouped data to different SSD erase blocks to reduce WAF, and improve overall SSD performance and lifetime. Our case study on the filebench benchmark demonstrates that our FDPFS prototype not only eases explicit data placement, but also yields up to 34% reduction in the SSD WAF which promises improved overall performance and lifetime of the SSD.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"349-352"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/LES.2024.3442927
Sunghoon Hong;Daejin Park
Autonomous mobile robots (AMRs) are widely used in dynamic warehouse environments for automated material handling, which is one of the fundamental parts of building intelligent logistics systems. A target docking system to transport materials, such as racks, carts, and pallets is an important technology for AMRs that directly affects production efficiency. In this letter, we propose a fast and precise rack detection algorithm based on 2-D LiDAR data for AMRs that consume power from batteries. This novel detection method based on machine learning to quickly detect various racks in a dynamic environment consists of three modules: first classification, secondary classification, and multiple-matching-based 2-D point cloud registration. We conducted various experiments to verify the rack detection performance of the existing and proposed methods in a low-power embedded system. As a result, the relative pose accuracy is improved and the inference speed is increased by about 3 times, which shows that the proposed method has faster inference speed while reducing the relative pose error.
{"title":"ML-Based Fast and Precise Embedded Rack Detection Software for Docking and Transport of Autonomous Mobile Robots Using 2-D LiDAR","authors":"Sunghoon Hong;Daejin Park","doi":"10.1109/LES.2024.3442927","DOIUrl":"https://doi.org/10.1109/LES.2024.3442927","url":null,"abstract":"Autonomous mobile robots (AMRs) are widely used in dynamic warehouse environments for automated material handling, which is one of the fundamental parts of building intelligent logistics systems. A target docking system to transport materials, such as racks, carts, and pallets is an important technology for AMRs that directly affects production efficiency. In this letter, we propose a fast and precise rack detection algorithm based on 2-D LiDAR data for AMRs that consume power from batteries. This novel detection method based on machine learning to quickly detect various racks in a dynamic environment consists of three modules: first classification, secondary classification, and multiple-matching-based 2-D point cloud registration. We conducted various experiments to verify the rack detection performance of the existing and proposed methods in a low-power embedded system. As a result, the relative pose accuracy is improved and the inference speed is increased by about 3 times, which shows that the proposed method has faster inference speed while reducing the relative pose error.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"401-404"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/LES.2024.3443881
Austin J. Bryant;Sercan Aygun
Hyperdimensional computing (HDC) has emerged as a promising paradigm offering lightweight yet powerful computing capabilities with inherent learning characteristics. By leveraging binary hyperdimensional vectors, HDC facilitates efficient and robust data processing, surpassing traditional machine learning (ML) approaches in terms of both speed and resilience. This letter addresses key challenges in HDC systems, particularly the conversion of data into the hyperdimensional domain and the integration of HDC with conventional ML frameworks. We propose a novel solution, the hyperdimensional vector quantized variational auto encoder (HDVQ-VAE), which seamlessly merges binary encodings with codebook representations in ML systems. Our approach significantly reduces memory overhead while enhancing training by replacing traditional codebooks with binary (−1, +1) counterparts. Leveraging this architecture, we demonstrate improved encoding-decoding procedures, producing high-quality images within acceptable peak signal-to-noise ratio (PSNR) ranges. Our work advances HDC by considering efficient ML system deployment to embedded systems.
{"title":"HDVQ-VAE: Binary Codebook for Hyperdimensional Latent Representations","authors":"Austin J. Bryant;Sercan Aygun","doi":"10.1109/LES.2024.3443881","DOIUrl":"https://doi.org/10.1109/LES.2024.3443881","url":null,"abstract":"Hyperdimensional computing (HDC) has emerged as a promising paradigm offering lightweight yet powerful computing capabilities with inherent learning characteristics. By leveraging binary hyperdimensional vectors, HDC facilitates efficient and robust data processing, surpassing traditional machine learning (ML) approaches in terms of both speed and resilience. This letter addresses key challenges in HDC systems, particularly the conversion of data into the hyperdimensional domain and the integration of HDC with conventional ML frameworks. We propose a novel solution, the hyperdimensional vector quantized variational auto encoder (HDVQ-VAE), which seamlessly merges binary encodings with codebook representations in ML systems. Our approach significantly reduces memory overhead while enhancing training by replacing traditional codebooks with binary (−1, +1) counterparts. Leveraging this architecture, we demonstrate improved encoding-decoding procedures, producing high-quality images within acceptable peak signal-to-noise ratio (PSNR) ranges. Our work advances HDC by considering efficient ML system deployment to embedded systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"325-328"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
RowHammer stands out as a prominent example, potentially the pioneering one, showcasing how a failure mechanism at the circuit level can give rise to a significant and pervasive security vulnerability within systems. Prior research has approached RowHammer attacks within a static threat model framework. Nonetheless, it warrants consideration within a more nuanced and dynamic model. This letter presents a low-overhead DRAM RowHammer vulnerability profiling technique, which utilizes innovative test vectors for categorizing memory cells into distinct security levels. The proposed test vectors intentionally weaken the spatial correlation between the aggressors and victim rows before an attack for evaluation, thus aiding designers in mitigating RowHammer vulnerabilities in the mapping phase. While there has been no previous research showcasing the impact of such profiling to our knowledge, our study methodically assesses 128 commercial DDR4 DRAM products. The results uncover the significant variability among chips from different manufacturers in the type and quantity of RowHammer attacks that can be exploited by adversaries.
{"title":"A Novel Insight Into the Vulnerability of DDR4 DRAM Cells Across Multiple Hammering Settings","authors":"Ranyang Zhou;Jacqueline Liu;Nakul Kochar;Sabbir Ahmed;Adnan Siraj Rakin;Shaahin Angizi","doi":"10.1109/LES.2024.3449232","DOIUrl":"https://doi.org/10.1109/LES.2024.3449232","url":null,"abstract":"RowHammer stands out as a prominent example, potentially the pioneering one, showcasing how a failure mechanism at the circuit level can give rise to a significant and pervasive security vulnerability within systems. Prior research has approached RowHammer attacks within a static threat model framework. Nonetheless, it warrants consideration within a more nuanced and dynamic model. This letter presents a low-overhead DRAM RowHammer vulnerability profiling technique, which utilizes innovative test vectors for categorizing memory cells into distinct security levels. The proposed test vectors intentionally weaken the spatial correlation between the aggressors and victim rows before an attack for evaluation, thus aiding designers in mitigating RowHammer vulnerabilities in the mapping phase. While there has been no previous research showcasing the impact of such profiling to our knowledge, our study methodically assesses 128 commercial DDR4 DRAM products. The results uncover the significant variability among chips from different manufacturers in the type and quantity of RowHammer attacks that can be exploited by adversaries.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"337-340"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/LES.2024.3445256
Jinyao Xu;Danny Abraham;Ian G. Harris
Return-oriented programming (ROP) have emerged as great threats to the modern embedded systems. ROP attacks can be used to either bypass credential verification or modify RAM contents. In this letter, we introduce a simple side-channel technique for the run-time ROP detection. We use processors’ power consumption pattern as an indicator for the potential ROP attacks, which can be deployed across different platforms. We avoid the computational complexities of training machine learning models by using a simple linear comparison algorithm to compare the known and unknown power patterns to discern anomalies. For evaluation, we implement both the ROP attacks in multiple scenarios on the benchmarks with various complexity levels. We demonstrate the robustness of our approach and also outline some potential overheads that the approach incurs for the run-time ROP detection.
{"title":"Run-Time ROP Attack Detection on Embedded Devices Using Side Channel Power Analysis","authors":"Jinyao Xu;Danny Abraham;Ian G. Harris","doi":"10.1109/LES.2024.3445256","DOIUrl":"https://doi.org/10.1109/LES.2024.3445256","url":null,"abstract":"Return-oriented programming (ROP) have emerged as great threats to the modern embedded systems. ROP attacks can be used to either bypass credential verification or modify RAM contents. In this letter, we introduce a simple side-channel technique for the run-time ROP detection. We use processors’ power consumption pattern as an indicator for the potential ROP attacks, which can be deployed across different platforms. We avoid the computational complexities of training machine learning models by using a simple linear comparison algorithm to compare the known and unknown power patterns to discern anomalies. For evaluation, we implement both the ROP attacks in multiple scenarios on the benchmarks with various complexity levels. We demonstrate the robustness of our approach and also outline some potential overheads that the approach incurs for the run-time ROP detection.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"377-380"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-05DOI: 10.1109/LES.2024.3440208
Rajat Bhattacharjya;Arnab Sarkar;Biswadip Maity;Nikil Dutt
Multiple signal classification (MUSIC) is a widely used direction of arrival (DoA)/angle of arrival (AoA) estimation algorithm applied to various application domains, such as autonomous driving, medical imaging, and astronomy. However, MUSIC is computationally expensive and challenging to implement in low-power hardware, requiring exploration of tradeoffs between accuracy, cost, and power. We present MUSIC-lite, which exploits approximate computing to generate a design space exploring accuracy-area-power tradeoffs. This is specifically applied to the computationally intensive singular value decomposition (SVD) component of the MUSIC algorithm in an orthogonal frequency-division multiplexing (OFDM) radar use case. MUSIC-lite incorporates approximate adders into the iterative CORDIC algorithm that is used for hardware implementation of MUSIC, generating interesting accuracy-area-power tradeoffs. Our experiments demonstrate MUSIC-lite’s ability to save an average of 17.25% on-chip area and 19.4% power with a minimal 0.14% error for efficient MUSIC implementations.
多信号分类（Multiple signal classification， MUSIC）是一种应用广泛的到达方向(DoA)/到达角（AoA）估计算法，应用于自动驾驶、医学成像、天文学等领域。然而，MUSIC在计算上是昂贵的，并且在低功耗硬件中实现具有挑战性，需要探索精度、成本和功耗之间的权衡。我们提出MUSIC-lite，它利用近似计算来生成一个探索精度-面积-功率权衡的设计空间。这特别适用于正交频分复用（OFDM）雷达用例中MUSIC算法的计算密集型奇异值分解（SVD）组件。MUSIC-lite将近似加法器集成到迭代CORDIC算法中，该算法用于MUSIC的硬件实现，生成了有趣的精度-面积-功率权衡。我们的实验证明了MUSIC-lite能够在有效的MUSIC实现中平均节省17.25%的片上面积和19.4%的功耗，最小误差为0.14%。
{"title":"MUSIC-Lite: Efficient MUSIC Using Approximate Computing: An OFDM Radar Case Study","authors":"Rajat Bhattacharjya;Arnab Sarkar;Biswadip Maity;Nikil Dutt","doi":"10.1109/LES.2024.3440208","DOIUrl":"https://doi.org/10.1109/LES.2024.3440208","url":null,"abstract":"Multiple signal classification (MUSIC) is a widely used direction of arrival (DoA)/angle of arrival (AoA) estimation algorithm applied to various application domains, such as autonomous driving, medical imaging, and astronomy. However, MUSIC is computationally expensive and challenging to implement in low-power hardware, requiring exploration of tradeoffs between accuracy, cost, and power. We present MUSIC-lite, which exploits approximate computing to generate a design space exploring accuracy-area-power tradeoffs. This is specifically applied to the computationally intensive singular value decomposition (SVD) component of the MUSIC algorithm in an orthogonal frequency-division multiplexing (OFDM) radar use case. MUSIC-lite incorporates approximate adders into the iterative CORDIC algorithm that is used for hardware implementation of MUSIC, generating interesting accuracy-area-power tradeoffs. Our experiments demonstrate MUSIC-lite’s ability to save an average of 17.25% on-chip area and 19.4% power with a minimal 0.14% error for efficient MUSIC implementations.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"329-332"},"PeriodicalIF":1.7,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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