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IEEE Embedded Systems Letters最新文献

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Time-Sensitive Networking in Low Latency Cyber-Physical Systems 低延迟网络物理系统中的时间敏感型网络连接
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-09-18 DOI: 10.1109/les.2024.3463545
Henrik Austad, Geir Mathisen
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引用次数: 0
FedTinyWolf -A Memory Efficient Federated Embedded Learning Mechanism FedTinyWolf - 一种内存高效的联合嵌入式学习机制
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-09-17 DOI: 10.1109/les.2024.3462638
Subhrangshu Adhikary, Subhayu Dutta
{"title":"FedTinyWolf -A Memory Efficient Federated Embedded Learning Mechanism","authors":"Subhrangshu Adhikary, Subhayu Dutta","doi":"10.1109/les.2024.3462638","DOIUrl":"https://doi.org/10.1109/les.2024.3462638","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"37 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142263901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators SCALLER：基于标准单元组装和局部布局效应的环形振荡器
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-09-12 DOI: 10.1109/les.2024.3459730
Muayad J. Aljafar, Zain Ul Abideen, Adriaan Peetermans, Benedikt Gierlichs, Samuel Pagliarini
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引用次数: 0
Comparing XML and JSON Characteristics as Formats for Data Serialisation Within Ultra-Low Power Embedded Systems 比较 XML 和 JSON 作为超低功耗嵌入式系统数据序列化格式的特点
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-08-28 DOI: 10.1109/les.2024.3450576
James Gerrans, R. Simon Sherratt
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引用次数: 0
IEEE Embedded Systems Letters Publication Information IEEE Embedded Systems Letters 出版信息
IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-08-28 DOI: 10.1109/LES.2024.3396921
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引用次数: 0
A Multi-Dimensional Hardware Trojan Design Platform to Enhance Hardware Security 提高硬件安全性的多维硬件木马设计平台
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-08-01 DOI: 10.1109/les.2024.3436701
Nilanjana Das, Mattis Hasler, Friedrich Pauls, Sebastian Haas
{"title":"A Multi-Dimensional Hardware Trojan Design Platform to Enhance Hardware Security","authors":"Nilanjana Das, Mattis Hasler, Friedrich Pauls, Sebastian Haas","doi":"10.1109/les.2024.3436701","DOIUrl":"https://doi.org/10.1109/les.2024.3436701","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"75 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity 基于方向纹理复杂性的嵌入式系统上优化的 Kvazaar 全内预测加速度
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-08-01 DOI: 10.1109/les.2024.3436511
James R. Majok, Mohammed Abo-Zahhad, Koji Inoue, Mohammed S. Sayed
{"title":"Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity","authors":"James R. Majok, Mohammed Abo-Zahhad, Koji Inoue, Mohammed S. Sayed","doi":"10.1109/les.2024.3436511","DOIUrl":"https://doi.org/10.1109/les.2024.3436511","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"106 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques 利用展开技术进行平方根计算的数字电路设计
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-07-29 DOI: 10.1109/les.2024.3435477
Ricardo Paez Villa, Jorge Rivera, Juan José Raygoza, Edwin Becerra, Susana Ortega
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引用次数: 0
On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix 论通过广度系数矩阵实现寄存器最小化的重定时
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-07-29 DOI: 10.1109/les.2024.3435388
H. Emmanuel Mu˜ noz, Jorge Rivera, Susana Ortega–Cisneros, Diego H. Gaytàn–Rivas
{"title":"On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix","authors":"H. Emmanuel Mu˜ noz, Jorge Rivera, Susana Ortega–Cisneros, Diego H. Gaytàn–Rivas","doi":"10.1109/les.2024.3435388","DOIUrl":"https://doi.org/10.1109/les.2024.3435388","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"159 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs 量化 CNN 的硬件感知贝叶斯神经架构搜索
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Embedded Systems Letters
Pub Date : 2024-07-26 DOI: 10.1109/les.2024.3434379
Mathieu Perrin, William Guicquero, Bruno Paille, Gilles Sicard
{"title":"Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs","authors":"Mathieu Perrin, William Guicquero, Bruno Paille, Gilles Sicard","doi":"10.1109/les.2024.3434379","DOIUrl":"https://doi.org/10.1109/les.2024.3434379","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"109 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141782194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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