A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-04-29 DOI:10.1109/TVLSI.2024.3392680

Yi-Hao Lan;Shen-Iuan Liu

引用次数: 0

Abstract

A 36-Gb/s

$2\times $

half-baud-rate (THBR) adaptive receiver (RX) is presented. The pattern-based adaptation method for adjusting the frequency response of a continuous-time linear equalizer (CTLE) is proposed. In addition, the reference voltage of the comparators is adapted to enhance the timing margin of the recovered clock in the RX. This THBR adaptive RX is fabricated in TSMC 28-nm CMOS technology with a core area of 0.097 mm2. The measured bit error rate (BER) is less than 10−12 for a 36-Gb/s pseudorandom binary sequence (PRBS) of 27 – 1, when the channel loss is 19 dB at 18 GHz. The total power consumption of this RX is 76 mW with gated adaptation circuits. The calculated figure of merit (FoM) is 2.1 pJ/bit.

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采用 28-nm CMOS 的 36-Gb/s 2$/times$ 半波特率自适应接收器

本文介绍了一种 36 Gb/s $2/times $ half-baud-rate (THBR) 自适应接收器（RX）。提出了基于模式的自适应方法，用于调整连续时间线性均衡器（CTLE）的频率响应。此外，还对比较器的基准电压进行了调整，以提高 RX 中恢复时钟的定时余量。这种 THBR 自适应 RX 采用台积电 28 纳米 CMOS 技术制造，核心面积为 0.097 平方毫米。当 18 GHz 信道损耗为 19 dB 时，36-Gb/s 的 27 - 1 伪随机二进制序列 (PRBS) 的实测误码率 (BER) 小于 10-12。该 RX 采用门控自适应电路，总功耗为 76 mW。计算得出的功耗（FoM）为 2.1 pJ/比特。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

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