Pub Date : 2025-02-25DOI: 10.1109/TVLSI.2025.3539514
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Pub Date : 2025-02-25DOI: 10.1109/TVLSI.2024.3520396
Mircea R. Stan
I am happy and honored to have been reappointed as Editor in Chief (EiC) for the IEEE Transactions on VLSI Systems (TVLSI) for another two-year term. As I continue my efforts to improve the quality of the journal, I am grateful for the renewed trust placed in me by the three IEEE sponsoring societies (CASS, SSCS and CS) and by the VLSI community at large. Contrary to a feared slowdown due to increased difficulties with scaling, the field of Very Large Scale Integration (VLSI) has actually grown at an increasingly fast rate as it provides the hardware backbone for the insatiable AI applications which are taking over the world. The H100/200 GPUs, which are essential for AI training, are the largest “conventional” integrated circuits (IC) with 80 billion transistors, while the wafer-scale WSE2/3, which can provide significant improvements in AI inference, are absolute behemoths with 4 trillion transistors! Mr. Moore can be proud there in heaven for what our industry is able to deliver!
{"title":"Editorial: Renewed Excellence for 2025–2026","authors":"Mircea R. Stan","doi":"10.1109/TVLSI.2024.3520396","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3520396","url":null,"abstract":"I am happy and honored to have been reappointed as Editor in Chief (EiC) for the IEEE Transactions on VLSI Systems (TVLSI) for another two-year term. As I continue my efforts to improve the quality of the journal, I am grateful for the renewed trust placed in me by the three IEEE sponsoring societies (CASS, SSCS and CS) and by the VLSI community at large. Contrary to a feared slowdown due to increased difficulties with scaling, the field of Very Large Scale Integration (VLSI) has actually grown at an increasingly fast rate as it provides the hardware backbone for the insatiable AI applications which are taking over the world. The H100/200 GPUs, which are essential for AI training, are the largest “conventional” integrated circuits (IC) with 80 billion transistors, while the wafer-scale WSE2/3, which can provide significant improvements in AI inference, are absolute behemoths with 4 trillion transistors! Mr. Moore can be proud there in heaven for what our industry is able to deliver!","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"603-626"},"PeriodicalIF":2.8,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903548","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-25DOI: 10.1109/TVLSI.2025.3539516
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2025.3539516","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3539516","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903516","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Presents corrections to the paper, (Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”).
{"title":"Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”","authors":"Peijun Ma;Ge Shang;Hongjin Liu;Jiangyi Shi;Weitao Pan;Yan Zhang;Yue Hao","doi":"10.1109/TVLSI.2025.3525903","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3525903","url":null,"abstract":"Presents corrections to the paper, (Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"902-902"},"PeriodicalIF":2.8,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10852349","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1109/TVLSI.2025.3527804
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2025.3527804","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3527804","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 2","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10849954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142992844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1109/TVLSI.2024.3523620
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3523620","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3523620","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 2","pages":"C2-C2"},"PeriodicalIF":2.8,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10849955","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142992850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-30DOI: 10.1109/TVLSI.2024.3517117
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3517117","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3517117","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818619","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142905766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-30DOI: 10.1109/TVLSI.2024.3517115
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3517115","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3517115","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"C2-C2"},"PeriodicalIF":2.8,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818572","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-27DOI: 10.1109/TVLSI.2024.3510682
Hasan Al Shaikh;Shuvagata Saha;Kimia Zamiri Azar;Farimah Farahmandi;Mark Tehranipoor;Fahim Rahman
Due to the increasingly complex interaction between the tightly integrated components, reuse of various untrustworthy third-party IPs (3PIPs), and security-unaware design practices, there have been a rising number of reports of system-on-chip (SoC) hardware (HW) vulnerabilities that compromise the security of critical assets. SoC security verification, therefore, is an indispensable part of the verification effort. The existing hardware verification methodologies either presuppose white-box knowledge or scale poorly with increasing design complexity. Hardware penetration testing (pentest) is an emerging gray-box security verification methodology at the register-transfer level (RTL) that is applicable across a wide variety of threat models and addresses many shortcomings of the existing methodologies. In this work, we propose Re-Pen, a novel hardware pentest framework that requires minimal gray-box information from the design specification to achieve significantly better security vulnerability (SV) detection performance than state-of-the-art pentest techniques. At the core of this framework lies a mutation engine that combines the strengths of reinforcement learning (RL) and binary particle swarm optimization (BPSO) in its test pattern mutation strategy to generate intelligent test patterns without manual supervision. This framework significantly reduces the requirement for detailed, manual, expertise-driven adaptations specific to the SoC under test. Through extensive experiments conducted on multiple SoCs, we demonstrate that Re-Pen can reduce vulnerability detection time by up to $3times $ and achieve a markedly improved consistency compared with the state of the art. Furthermore, Re-Pen was able to detect native security bugs in an open-source SoC. It successfully identified a scenario where, despite a functionally correct hardware implementation, a mistake in the architectural specification allowed privilege escalation from the software layer.
{"title":"Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification","authors":"Hasan Al Shaikh;Shuvagata Saha;Kimia Zamiri Azar;Farimah Farahmandi;Mark Tehranipoor;Fahim Rahman","doi":"10.1109/TVLSI.2024.3510682","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3510682","url":null,"abstract":"Due to the increasingly complex interaction between the tightly integrated components, reuse of various untrustworthy third-party IPs (3PIPs), and security-unaware design practices, there have been a rising number of reports of system-on-chip (SoC) hardware (HW) vulnerabilities that compromise the security of critical assets. SoC security verification, therefore, is an indispensable part of the verification effort. The existing hardware verification methodologies either presuppose white-box knowledge or scale poorly with increasing design complexity. Hardware penetration testing (pentest) is an emerging gray-box security verification methodology at the register-transfer level (RTL) that is applicable across a wide variety of threat models and addresses many shortcomings of the existing methodologies. In this work, we propose Re-Pen, a novel hardware pentest framework that requires minimal gray-box information from the design specification to achieve significantly better security vulnerability (SV) detection performance than state-of-the-art pentest techniques. At the core of this framework lies a mutation engine that combines the strengths of reinforcement learning (RL) and binary particle swarm optimization (BPSO) in its test pattern mutation strategy to generate intelligent test patterns without manual supervision. This framework significantly reduces the requirement for detailed, manual, expertise-driven adaptations specific to the SoC under test. Through extensive experiments conducted on multiple SoCs, we demonstrate that Re-Pen can reduce vulnerability detection time by up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> and achieve a markedly improved consistency compared with the state of the art. Furthermore, Re-Pen was able to detect native security bugs in an open-source SoC. It successfully identified a scenario where, despite a functionally correct hardware implementation, a mistake in the architectural specification allowed privilege escalation from the software layer.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"853-866"},"PeriodicalIF":2.8,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The existing hardware Trojan (HT) detection technology usually relies on the golden reference model. With the continuous improvement of circuit integration, the detection accuracy of traditional methods such as side-channel analysis has declined. Methods based on testability and switch probability analysis have shown high detection accuracy. However, these techniques have a limited detection scope and are generally ineffective at identifying HT where the Sandia controllability/observability analysis program (SCOAP) values or switch probabilities are similar to those of normal signals. Against this backdrop, this article proposes a detection method based on graph neural networks (GNNs), which can achieve HT detection at the register transfer level (RTL) without the golden reference model. First, the RTL code is transformed into a data flow graph (DFG), and node feature extraction and node label marking are carried out during the transformation process. To mitigate the impact of insufficient initial features on the GNN model performance, the node feature vector used in this article comprises 37-D node types and 6-D structural features such as the minimum distance from the primary input (PI) and primary output (PO), in-degree, and out-degree. Subsequently, several GNN models are built for node classification tasks. The best model achieves an average of 99.1% recall and 96.7% F1-score on the open-source dataset on the Trust-Hub platform. Compared to the state-of-the-art detection results at RTL, the F1-score in this article has increased by an average of 3.8%.
{"title":"GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features","authors":"Peijun Ma;Ge Shang;Hongjin Liu;Jiangyi Shi;Weitao Pan;Yan Zhang;Yue Hao","doi":"10.1109/TVLSI.2024.3513218","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3513218","url":null,"abstract":"The existing hardware Trojan (HT) detection technology usually relies on the golden reference model. With the continuous improvement of circuit integration, the detection accuracy of traditional methods such as side-channel analysis has declined. Methods based on testability and switch probability analysis have shown high detection accuracy. However, these techniques have a limited detection scope and are generally ineffective at identifying HT where the Sandia controllability/observability analysis program (SCOAP) values or switch probabilities are similar to those of normal signals. Against this backdrop, this article proposes a detection method based on graph neural networks (GNNs), which can achieve HT detection at the register transfer level (RTL) without the golden reference model. First, the RTL code is transformed into a data flow graph (DFG), and node feature extraction and node label marking are carried out during the transformation process. To mitigate the impact of insufficient initial features on the GNN model performance, the node feature vector used in this article comprises 37-D node types and 6-D structural features such as the minimum distance from the primary input (PI) and primary output (PO), in-degree, and out-degree. Subsequently, several GNN models are built for node classification tasks. The best model achieves an average of 99.1% recall and 96.7% F1-score on the open-source dataset on the Trust-Hub platform. Compared to the state-of-the-art detection results at RTL, the F1-score in this article has increased by an average of 3.8%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"831-840"},"PeriodicalIF":2.8,"publicationDate":"2024-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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