{"title":"A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation","authors":"Tiedong Cheng, Hao Rao, Jinxiang Wei","doi":"10.1016/j.vlsi.2024.102209","DOIUrl":null,"url":null,"abstract":"<div><p>A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the <span><math><mrow><mo>Δ</mo><msub><mi>V</mi><mrow><mi>G</mi><mi>S</mi></mrow></msub></mrow></math></span> of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2024-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926024000737","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.