Design and Optimization of a Heterojunction (Ge/Si) Vertical-Tunnel Field Effect Transistor (HV-TFET) with a Doped Bar for Low-Power Applications

Abstract

Tunnel field effect transistors (TFETs) are known for lower power requirements than MOSFETs due to their utilization of the band-to-band tunneling mechanism, along with low subthreshold swing (SS). The traditional TFET suffers from low drain current; however, drain current can be improved by modifying the TFET device structure. In this work, a 2-D heterojunction (Ge/Si) vertical-tunnel field effect transistor (HV-TFET) with an optimal design is proposed in which the source region is made of germanium (Ge) due to its low bandgap, while silicon (Si) is used for the regions of drain and channel to mitigate leakage current because of its wider bandgap. The goal of this work is to achieve improved switching by enhancing the ON-state current (I_ON) and reducing the OFF-state current (I_OFF). The currents obtained have values of 1.19 × 10⁻³ A/µm and ~ 10⁻¹⁵ A/µm, respectively, and therefore the I_ON/I_OFF ratio is ~ 10¹¹ for the device proposed in this paper. Three different dielectric gate oxide materials are used for studying the effect of dielectric materials on the device parameters. Hafnium oxide (HfO₂) is found to offer the best results when used for gate oxide, and hence is used in the proposed device structure. Also, this work examines a number of electrical parameters of the device structure due to changes in physical device parameters. The results are produced using the Sentaurus TCAD tool to confirm the suitability of the proposed device for use in circuit applications with low-power strategies.