Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

Abstract

This study presents a straightforward approach for fabricating heterogeneous complementary FET (CFET) devices. The process flow commences with a SiGe/Ge/Si epitaxial multilayer structure grown on a SOI substrate. The source/drains for both stacked devices were straightforwardly performed through P and B implantations with precise depth control, respectively. The isolation of the top p-SiGe FET from the bottom n-Si FET was achieved by etching away the middle Ge sacrificial layer and subsequently filled with SiO₂ dielectric material. The etching selectivity of Ge over Si and Si_0.8Ge_0.2 by utilizing a H₂O₂ solution was nearly infinite, resulting in a flawless structure with p-SiGe channels stacked over n-Si channels. Finally, a functional CFET inverter device composed of a top inversion mode (IM) SiGe nanosheet pFET and a bottom IM Si nanosheet nFET was demonstrated.